Abstract: The disclosure relates to a solar module, which includes a plurality of solar cells which are interconnected to generate a direct-voltage power at module terminals, and a receiving unit for receiving an accurate time signal. The solar module further includes a communication unit for the synchronous transmission of the received accurate time signal to an inverter. The inverter is connected to the solar module by means of direct-voltage lines. The disclosure also relates to an assembly that can be integrated into a solar module, and to an energy generation system having a solar module of this type.

Abstract: An unfolding bridge includes a half-bridge with a first input terminal, a second input terminal, and an output terminal, wherein the half-bridge includes a first bridge switch connected between the first input terminal and the output terminal and a second bridge switch connected between the second input terminal and the output terminal. The unfolding bridge also includes a further half-bridge which includes a first further bridge switch connected between the first input terminal and a further output terminal and a second further bridge switch connected between the second input terminal and the further output terminal. A switch controller for operation of the bridge switches is designed such that a connection of the output terminals with the input terminals via the bridge switches is reversed at a zero crossing of an alternating current flowing at the output terminals.

Abstract: An unfolding bridge includes a half-bridge with a first input terminal, a second input terminal, and an output terminal, wherein the half-bridge includes a first bridge switch connected between the first input terminal and the output terminal and a second bridge switch connected between the second input terminal and the output terminal. The unfolding bridge also includes a further half-bridge which includes a first further bridge switch connected between the first input terminal and a further output terminal and a second further bridge switch connected between the second input terminal and the further output terminal. A switch controller for operation of the bridge switches is designed such that a connection of the output terminals with the input terminals via the bridge switches is reversed at a zero crossing of an alternating current flowing at the output terminals.

Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

Abstract: In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether the current state of the data stored by the plurality of capacitors corresponds to the initial state. The circuitry inverts the data read out of the memory array during a read operation when the current state of the data does not correspond to the initial state.

Abstract: A method for forming an integrated circuit having openings in a mold layer and for producing capacitors is disclosed. In one embodiment, nanotubes or nanowires are grown vertically on a horizontal substrate surface. The nanotubes or nanowires serve as a template for forming openings in a mold layer. The substrate is covered with a mold material after the formation of the nanowires or nanotubes. One embodiment provides mold layers having openings with a much higher aspect ratio.

Abstract: One implementation is a method for fabricating a semiconductor on a substrate. A first layer is formed on the substrate. An implanted pattern is introduced into the first layer by implanting using a structured implantation mask arranged over the first layer. A structured second layer is formed on the first layer after removing the implantation mask. A first pattern is generated in the substrate using the second layer as a mask. The first layer is developed with regard to the implanted pattern. A second pattern is generated in the substrate using the first layer as a mask.

Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

Abstract: In one embodiment, an integrated circuit includes a memory array having a plurality of capacitors for storing data of an initial state in the memory array in an initial state. The integrated circuit also includes circuitry for occasionally inverting the data stored by the plurality of capacitors and tracking whether the current state of the data stored by the plurality of capacitors corresponds to the initial state. The circuitry inverts the data read out of the memory array during a read operation when the current state of the data does not correspond to the initial state.

Abstract: On aspect is a method to manufacture an integrated circuit including a reshaping process of the wafer edge region and an apparatus to perform the reshaping process.

Abstract: An integrated circuit having a memory arrangement including capacitor elements and further capacitor elements is disclosed. One embodiment provides a substrate layer with contact pads and further contact pads; the capacitor elements being disposed in a first level on the substrate layer and connected with the contact pads; the further capacitor elements being disposed in a second level above the first level; contact elements being disposed between the capacitor elements and connected with the further contact pads; the further capacitor elements being disposed above the contact elements and being connected with the contact elements.

Abstract: A method for forming an integrated circuit having openings in a mold layer and for producing capacitors is disclosed. In one embodiment, nanotubes or nanowires are grown vertically on a horizontal substrate surface. The nanotubes or nanowires serve as a template for forming openings in a mold layer. The substrate is covered with a mold material after the formation of the nanowires or nanotubes. One embodiment provides mold layers having openings with a much higher aspect ratio.

Abstract: A method of determining the endpoint of a planarizing process is disclosed. An endpoint detection signal is selectively sampled from at least one predetermined location within a planarizing region defined on a planarizing web. Planarization is stopped when the endpoint criterion based on the endpoint detection signal is detected.

Abstract: A process for planarizing a process layer having structures and has been applied to a working surface of a semiconductor device, includes abrading the process layer down to the working surface using a polishing device. The working surface is planarized, and a defect density in the working surface is minimized and the polishing process is topology-independent.

Abstract: A method and apparatus of planarizing substrates is disclosed. A planarizing web medium is prepared for planarizing substrates to reduce defect generation. The planarizing web has a planarizing region and preparing region defined thereon, wherein at least one portion of the preparing region is outside the planarizing region. The web medium is advanced to move one portion of the web out of the planarizing region and another portion into the planarizing region.

Abstract: The optimization of a CMP process provides the use of an auxiliary layer (4) between a dielectric (1) in the vicinity of patterned portions and a layer of a liner (2). If the liner (2) is perforated in the CMP process, then the undercutting of the liner (2) by the chemical removal of the auxiliary layer (4) simplifies the process overall. Advantages are significantly lower defect densities due to CMP scratches, fewer short circuits, fewer alignment errors.

Abstract: A method and apparatus of planarizing substrates is disclosed. A planarizing web medium is prepared for planarizing substrates to reduce defect generation. The planarizing web has a planarizing region and preparing region defined thereon, wherein at least one portion of the preparing region is outside the planarizing region. The web medium is advanced to move one portion of the web out of the planarizing region and another portion into the planarizing region.

Abstract: A method of determining the endpoint of a planarizing process is disclosed. An endpoint detection signal is selectively sampled from at least one predetermined location within a planarizing region defined on a planarizing web. Planarization is stopped when the endpoint criterion based on the endpoint detection signal is detected.

Abstract: A method and a semiconductor wafer configuration for producing an alignment mark for semiconductor wafers. In the method, an alignment mark region surrounded by a metal frame is formed on the semiconductor wafer. Subsequently, the alignment mark region and the metal frame are completely buried in at least one dielectric layer, in order to define an alignment mark area in the alignment mark region on the dielectric layer with a photolithography process. The boundary of the alignment mark area lies at a uniform distance within the boundary of the alignment mark region, defined by the metal frame. Subsequently (to uncover the alignment mark area by an anisotropic etching of the dielectric layer), the etching depth is defined in such a way that the alignment mark opening extends at least as far as the level of the metal frame.

Abstract: A substrate holder is described which has a movable plate elastically mounted inside a main body. With the substrate holder, a polishing operation can be performed in two basic operation modes corresponding to two different vertical end positions of the movable plate. In a first (downward) mode the movable plate stays in mechanical contact with the substrate whereas in a second (upward) mode an air cushion is generated in a chamber between the movable plate and the substrate for pressurizing the substrate onto the polishing pad.