Abstract: A hardware accelerator is disclosed for performing a computational operation in a cryptographic application comprises one or more addressable computational blocks and a plurality of addressable register blocks. A bus is used for data exchange between the blocks in the form of read-from-bus operations and write-to-bus operations in the course of performing the computational operation. A controller for controlling the data exchange performs a block addressing operation using a respective pre-assigned first address of the blocks for addressing the one or more of the blocks involved in a write-to-bus operation in the data exchange. The controller performs a dummy-addressing selection operation to select one or more of the blocks for a dummy addressing operation and a dummy-addressing operation of the selected one or more of the blocks for dummy-addressing the one or more of the selected blocks in the write-to-bus operation.

Abstract: The invention relates to a method for the exchange of personal information in non-trusted peer-to-peer environments in a step-by-step fashion, in which the information preferably prepared as a graphics display is segmented into several individual sections and is subsequently alternately exchanged between the communication partners.

Abstract: The present invention relates to a protocol accelerator module for a data transmission protocol level of a transceiver, particularly but not exclusively for rapid forwarding of data packets in wireless sensor networks using the time-division multiple access method according to the IEEE 802.15.4 standard. The invention also relates to a method of transceiver operation for rapid forwarding of data packets, likewise particularly, but not exclusively, in wireless sensor networks using the time-division multiple access method according to the IEEE 802.15.4 standard. The core of the invention is a reference table which stores references from identifiers of second transceivers to identifiers of third transceivers as well as references from specific messages to identifiers of third transceivers. A transceiver can check during reception of a data packet whether it is a data packet to be forwarded, and can take appropriate precautions for rapid sending of a data packet to be forwarded.

Abstract: Safeguarding communication channels is required in particular in wireless networks. The use of encryption mechanisms in the form of software is limited by the required calculation and energy capacities of mobile terminals. Costs are of significance when using hardware solutions for cryptographic operations. The present invention provides an approach which simultaneously tackles all those points. It concerns a hardware accelerator for polynomial multiplication in extended Galois fields (GF), wherein the per se known Karatsuba method is iteratively applied in accordance with the invention. When using the invention the area requirement can be reduced for example from 6.2 mm2 to 2.1 mm2. The solution according to the invention also reduces the energy consumption in comparison with solutions in accordance with the state of the art by 30%.

Abstract: The present invention relates to a protocol accelerator module for a data transmission protocol level of a transceiver, particularly but not exclusively for rapid forwarding of data packets in wireless sensor networks using the time-division multiple access method according to the IEEE 802.15.4 standard. The invention also relates to a method of transceiver operation for rapid forwarding of data packets, likewise particularly, but not exclusively, in wireless sensor networks using the time-division multiple access method according to the IEEE 802.15.4 standard. The core of the invention is a reference table which stores references from identifiers of second transceivers to identifiers of third transceivers as well as references from specific messages to identifiers of third transceivers. A transceiver can check during reception of a data packet whether it is a data packet to be forwarded, and can take appropriate precautions for rapid sending of a data packet to be forwarded.

Abstract: A method of reducing a first data word corresponding to a polynomial C(x) and having a length of a maximum of 2n?1 to a second data word of a length of a maximum m which in a binary finite field GF(2m) whose elements are of a maximum length m corresponds to a polynomial C?0(x) equivalent to C(x), wherein m is smaller than or equal to n, includes partitioning of the first data word into a binary first sub-data word C0 and a binary second sub-data word C1, repeated right-shift of C1 to form summand terms until a respective summand term is associated with each non-disappearing term of a reduction trinomial or pentanomial which is not the term xm, adding the summand terms formed to the first sub-data word to form a sum data word and applying the partitioning step to the summand data word formed until the ascertained sum data word is of a length of a maximum m and forms the desired second data word.

Abstract: Safeguarding communication channels is required in particular in wireless networks. The use of encryption mechanisms in the form of software is limited by the required calculation and energy capacities of mobile terminals. Costs are of significance when using hardware solutions for cryptographic operations. The present invention provides an approach which simultaneously tackles all those points. It concerns a hardware accelerator for polynomial multiplication in extended Galois fields (GF), wherein the per se known Karatsuba method is iteratively applied in accordance with the invention. When using the invention the area requirement can be reduced for example from 6.2 mm2 to 2.1 mm2. The solution according to the invention also reduces the energy consumption in comparison with solutions in accordance with the state of the art by 30%.