Abstract: A hardware accelerator is disclosed for performing a computational operation in a cryptographic application comprises one or more addressable computational blocks and a plurality of addressable register blocks. A bus is used for data exchange between the blocks in the form of read-from-bus operations and write-to-bus operations in the course of performing the computational operation. A controller for controlling the data exchange performs a block addressing operation using a respective pre-assigned first address of the blocks for addressing the one or more of the blocks involved in a write-to-bus operation in the data exchange. The controller performs a dummy-addressing selection operation to select one or more of the blocks for a dummy addressing operation and a dummy-addressing operation of the selected one or more of the blocks for dummy-addressing the one or more of the selected blocks in the write-to-bus operation.

Abstract: A cryptoprocessor has a processor core for receiving and executing instructions of a program code based on a program flow chart, a program memory unit which stores the program code with instructions in an individually encrypted format, wherein the respective instructions contain at least one instruction data word and an instruction data key allocated to the respective instruction, a respective instruction is encrypted using a program data key and the instruction data key of a respective preceding instruction, which is to be executed immediately beforehand in accordance with the program flow chart, and wherein the same instruction data key is allocated to the corresponding possible preceding instructions only in the event that a corresponding instruction in the program flow chart has a plurality of possible preceding instructions, the respective instruction data keys otherwise being unique to the instruction. A decryption unit is also described.

Abstract: A cryptoprocessor has a processor core for receiving and executing instructions of a program code based on a program flow chart, a program memory unit which stores the program code with instructions in an individually encrypted format, wherein the respective instructions contain at least one instruction data word and an instruction data key allocated to the respective instruction, a respective instruction is encrypted using a program data key and the instruction data key of a respective preceding instruction, which is to be executed immediately beforehand in accordance with the program flow chart, and wherein the same instruction data key is allocated to the corresponding possible preceding instructions only in the event that a corresponding instruction in the program flow chart has a plurality of possible preceding instructions, the respective instruction data keys otherwise being unique to the instruction. A decryption unit is also described.

Abstract: A device for multiplying two bit sequences has a controller that selects and activates exactly one multiplier unit from a plurality of parallel multiplier units, according to a random signal. A partial multiplier unit shared by all the multiplier units receives and multiplies operands formed by the respectively activated multiplier unit. Each multiplier unit implements a different multiplication method with a respective selector unit that selects segments of the bit sequences to be multiplied, in accordance with a selection plan adapted to the respective multiplication method, to form operands from one or more segments and outputs the operands. The respective accumulation unit receives step by step partial products from the partial multiplier unit, accumulates the partial products in accordance with an accumulation plan adapted to the implemented multiplication method and matching the selection plan, and outputs the calculated product of after accumulation has been completed.

Abstract: A device for multiplying two bit sequences has a controller that selects and activates exactly one multiplier unit from a plurality of parallel multiplier units, according to a random signal. A partial multiplier unit shared by all the multiplier units receives and multiplies operands formed by the respectively activated multiplier unit. Each multiplier unit implements a different multiplication method with a respective selector unit that selects segments of the bit sequences to be multiplied, in accordance with a selection plan adapted to the respective multiplication method, to form operands from one or more segments and outputs the operands. The respective accumulation unit receives step by step partial products from the partial multiplier unit, accumulates the partial products in accordance with an accumulation plan adapted to the implemented multiplication method and matching the selection plan, and outputs the calculated product of after accumulation has been completed.

Abstract: A semiconductor device, in particular an integrated circuit with protection against side channel attacks, in particular imaging- and probing-based attacks, EMA and reverse engineering, in which a metallic conductive layer of a first (104) and/or a second potential supply line (106) are each connected directly and individually to all the circuit components via respective individual conductor path structures (V1, V2).

Abstract: A semiconductor device, in particular an integrated circuit with protection against side channel attacks, in particular imaging- and probing-based attacks, EMA and reverse engineering, in which a metallic conductive layer of a first (104) and/or a second potential supply line (106) are each connected directly and individually to all the circuit components via respective individual conductor path structures (V1, V2).

Abstract: The invention relates to a method for the exchange of personal information in non-trusted peer-to-peer environments in a step-by-step fashion, in which the information preferably prepared as a graphics display is segmented into several individual sections and is subsequently alternately exchanged between the communication partners.

Abstract: The present invention relates to a protocol accelerator module for a data transmission protocol level of a transceiver, particularly but not exclusively for rapid forwarding of data packets in wireless sensor networks using the time-division multiple access method according to the IEEE 802.15.4 standard. The invention also relates to a method of transceiver operation for rapid forwarding of data packets, likewise particularly, but not exclusively, in wireless sensor networks using the time-division multiple access method according to the IEEE 802.15.4 standard. The core of the invention is a reference table which stores references from identifiers of second transceivers to identifiers of third transceivers as well as references from specific messages to identifiers of third transceivers. A transceiver can check during reception of a data packet whether it is a data packet to be forwarded, and can take appropriate precautions for rapid sending of a data packet to be forwarded.

Abstract: A cryptography device which reduces side channel information including a first computing block adapted to either encrypt or decrypt received first input data and to output the encrypted or decrypted first input data as first output data at a first data output, a second computing block adapted to either encrypt or decrypt received second input data and to output the encrypted or decrypted second input data as second output data at a second data output, and a control unit connected to the first and second computing blocks and adapted in a first operating condition on the one hand to partially or completely assign the first output data to the first computing block as the first input data and on the other hand to completely or partially assign the first output data to the second computing block as part of the second input data.

Abstract: A cryptography device which reduces side channel information including a first computing block adapted to either encrypt or decrypt received first input data and to output the encrypted or decrypted first input data as first output data at a first data output, a second computing block adapted to either encrypt or decrypt received second input data and to output the encrypted or decrypted second input data as second output data at a second data output, and a control unit connected to the first and second computing blocks and adapted in a first operating condition on the one hand to partially or completely assign the first output data to the first computing block as the first input data and on the other hand to completely or partially assign the first output data to the second computing block as part of the second input data.

Abstract: The present invention relates to a protocol accelerator module for a data transmission protocol level of a transceiver, particularly but not exclusively for rapid forwarding of data packets in wireless sensor networks using the time-division multiple access method according to the IEEE 802.15.4 standard. The invention also relates to a method of transceiver operation for rapid forwarding of data packets, likewise particularly, but not exclusively, in wireless sensor networks using the time-division multiple access method according to the IEEE 802.15.4 standard. The core of the invention is a reference table which stores references from identifiers of second transceivers to identifiers of third transceivers as well as references from specific messages to identifiers of third transceivers. A transceiver can check during reception of a data packet whether it is a data packet to be forwarded, and can take appropriate precautions for rapid sending of a data packet to be forwarded.

Abstract: A cryptography device which reduces side channel information including a first computing block adapted to either encrypt or decrypt received first input data and to output the encrypted or decrypted first input data as first output data at a first data output, a second computing block adapted to either encrypt or decrypt received second input data and to output the encrypted or decrypted second input data as second output data at a second data output, and a control unit connected to the first and second computing blocks and adapted in a first operating condition on the one hand to partially or completely assign the first output data to the first computing block as the first input data and on the other hand to completely or partially assign the first output data to the second computing block as part of the second input data.

Abstract: A method of reducing a first data word corresponding to a polynomial C(x) and having a length of a maximum of 2n?1 to a second data word of a length of a maximum m which in a binary finite field GF(2m) whose elements are of a maximum length m corresponds to a polynomial C?0(x) equivalent to C(x), wherein m is smaller than or equal to n, includes partitioning of the first data word into a binary first sub-data word C0 and a binary second sub-data word C1, repeated right-shift of C1 to form summand terms until a respective summand term is associated with each non-disappearing term of a reduction trinomial or pentanomial which is not the term xm, adding the summand terms formed to the first sub-data word to form a sum data word and applying the partitioning step to the summand data word formed until the ascertained sum data word is of a length of a maximum m and forms the desired second data word.

Abstract: Process for the gradual exchange of personal information in non-trusted peer-to-peer environments. Information, preferably prepared as graphical representations, is decomposed into a plurality of individual parts, then alternatively exchanged between the communication partners.