Patents by Inventor Peter Leaback

Peter Leaback has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120118380
    Abstract: A solar reflective fibre having a longitudinal axis, the fibre comprising: a substantially continuous primary portion having a first refractive index; and a plurality of secondary portions, each secondary portion having a second refractive index different from the first refractive index. The primary and secondary portions are arranged to run substantially continuously along at least a portion of a length of the fibre, the primary portion providing a host medium within which the secondary portions are provided. The primary and secondary portions are arranged to constitute a dielectric mirror structure whereby a phase of a plurality of scattered beams of radiation each beam being scattered at one of a plurality of respective interfaces between primary and secondary portions interfere constructively with one another thereby to reduce an amount of radiation transmitted through the fibre.
    Type: Application
    Filed: July 30, 2010
    Publication date: May 17, 2012
    Inventor: Peter Leaback
  • Patent number: 7904702
    Abstract: A multi-threaded processor determines which threads to execute, switches between execution of threads in dependence on the determination, each thread being coupled to a respective register for storing the state of the thread and used in executing instructions on the thread and includes a further register shared by all the threads. The executing threads use the further register to improve execution performance and prevents the switching of execution to another thread while the internal register is in use.
    Type: Grant
    Filed: August 13, 2008
    Date of Patent: March 8, 2011
    Assignee: Imagination Technologies Limited
    Inventors: Peter Leaback, Morrie Berglas
  • Publication number: 20100111180
    Abstract: There is provided a method and apparatus for scene change detection for use with bit-rate control of a video compression system. The method and apparatus may be used for scene change detection in intra-coded and/or inter-coded pictures. The method comprises the steps of: compressing each picture in a video signal in turn; determining complexity data from the compressed signal for each picture after partial compression of the picture; determining from the complexity data whether a scene change may have taken place; and adjusting the compression step and allocated compressed bit number for pictures after a scene change detection in dependence on the result of the determination. For an intra-coded picture, the complexity data is a monotonically increasing function of a quantisation parameter and a compressed bit number used in the compression step for the partial compression from which the complexity data is determined.
    Type: Application
    Filed: April 28, 2009
    Publication date: May 6, 2010
    Inventors: John Gao, Peter Leaback, Mingyou Hu
  • Publication number: 20090063824
    Abstract: A multi-threaded processor determines which threads to execute, switches between execution of threads in dependence on the determination, each thread being coupled to a respective register for storing the state of the thread and used in executing instructions on the thread and includes a further register shared by all the threads. The executing threads use the further register to improve execution performance and prevents the switching of execution to another thread while the internal register is in use.
    Type: Application
    Filed: August 13, 2008
    Publication date: March 5, 2009
    Inventors: Peter Leaback, Morrie Berglas
  • Publication number: 20060047886
    Abstract: A memory controller maps a processor generated address to a banked DRAM address by applying a randomising function which results in the banks appearing in an irregular and non-cyclic order in the conceptual memory map. Incremental addressing by two or more requestors is thereby more evenly distributed amongst the banks of DRAM to improve average access speed.
    Type: Application
    Filed: August 12, 2005
    Publication date: March 2, 2006
    Inventor: Peter Leaback
  • Publication number: 20050206786
    Abstract: A motion compensation deinterlacer for producing a progressive scan signal from an interlaced signal, wherein a motion compensation means derives missing lines in an interlaced field from at least one other field in the interlaced signal; a means derives a first confidence measure for the accuracy of the motion compensation means using the known lines of the field for which missing lines are to be derived; a means derives a second confidence measure for the accuracy of the motion compensation unit using known lines of at least two other fields; and a means selects outputs for display from at least the motion compensation unit and one other deinterlacing means in dependence on the result of the comparison.
    Type: Application
    Filed: September 29, 2004
    Publication date: September 22, 2005
    Inventor: Peter Leaback