Abstract: The invention relates to a DEPFET comprising: a semiconductor substrate (100) of a first conduction type, which has a first main surface (101) and a second main surface (102), which are opposite one another; a source terminal region (1s) of a second conduction type on the first main surface (101); a drain terminal region (1d) of a second conduction type; a channel region (10), which is arranged between the source terminal region (1s) and the drain terminal region (1d); a gate electrode (11), which is separated from the channel region (10) by a gate insulator (6); a rear activation region (104) of a second conduction type, which is formed on the second main surface (102); and a substrate doping increase region (2) of a first conduction type, which is formed at least under the source terminal region (1s) and under the channel region (10), the substrate doping increase region (2) having a signal charge control region (20) of the first conduction type below the gate electrode (11), in which signal charge control

Abstract: The invention relates to a DEPFET comprising: a semiconductor substrate (100) of a first conduction type, which has a first main surface (101) and a second main surface (102), which are opposite one another; a source terminal region (1s) of a second conduction type on the first main surface (101); a drain terminal region (1d) of a second conduction type; a channel region (10), which is arranged between the source terminal region (1s) and the drain terminal region (1d); a gate electrode (11), which is separated from the channel region (10) by a gate insulator (6); a rear activation region (104) of a second conduction type, which is formed on the second main surface (102); and a substrate doping increase region (2) of a first conduction type, which is formed at least under the source terminal region (1s) and under the channel region (10), the substrate doping increase region (2) having a signal charge control region (20) of the first conduction type below the gate electrode (11), in which signal charge control

Abstract: The invention relates to a DEPFET comprising: a semiconductor substrate (100) of a first conduction type, which has a first main surface (101) and a second main surface (102), which are opposite one another; a source terminal region (1s) of a second conduction type on the first main surface (101); a drain terminal region (1d) of a second conduction type; a channel region (10), which is arranged between the source terminal region (1s) and the drain terminal region (1d); a gate electrode (11), which is separated from the channel region (10) by a gate insulator (6); a rear activation region (104) of a second conduction type, which is formed on the second main surface (102); and a substrate doping increase region (2) of a first conduction type, which is formed at least under the source terminal region (1s) and under the channel region (10), the substrate doping increase region (2) having a signal charge control region (20) of the first conduction type below the gate electrode (11), in which signal charge control

Abstract: The invention relates to a DEPFET comprising: a semiconductor substrate (100) of a first conduction type, which has a first main surface (101) and a second main surface (102), which are opposite one another; a source terminal region (1s) of a second conduction type on the first main surface (101); a drain terminal region (1d) of a second conduction type; a channel region (10), which is arranged between the source terminal region (1s) and the drain terminal region (1d); a gate electrode (11), which is separated from the channel region (10) by a gate insulator (6); a rear activation region (104) of a second conduction type, which is formed on the second main surface (102); and a substrate doping increase region (2) of a first conduction type, which is formed at least under the source terminal region (1s) and under the channel region (10), the substrate doping increase region (2) having a signal charge control region (20) of the first conduction type below the gate electrode (11), in which signal charge control

Abstract: The invention relates to a DEPFET comprising: a semiconductor substrate (100) of a first conduction type, which has a first main surface (101) and a second main surface (102), which are opposite one another; a source terminal region (1s) of a second conduction type on the first main surface (101); a drain terminal region (1d) of a second conduction type; a channel region (10), which is arranged between the source terminal region (1s) and the drain terminal region (1d); a gate electrode (11), which is separated from the channel region (10) by a gate insulator (6); a rear activation region (104) of a second conduction type, which is formed on the second main surface (102); and a substrate doping increase region (2) of a first conduction type, which is formed at least under the source terminal region (1s) and under the channel region (10), the substrate doping increase region (2) having a signal charge control region (20) of the first conduction type below the gate electrode (11), in which signal charge control

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor mesa having source zones arranged along a longitudinal axis of the semiconductor mesa and at least one body zone forming first pn junctions with the source zones and a second pn junction with a drift zone. The semiconductor device further includes stripe-shaped electrode structures on opposite sides of the semiconductor mesa and separation regions between neighboring ones of the source zones. At least one of the electrode structures includes a gate electrode. In the separation regions, at least one of (i) a capacitive coupling between the gate electrode and the semiconductor mesa and (ii) a conductivity of majority charge carriers of the drift zone is lower than outside of the separation regions.

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor mesa having source zones arranged along a longitudinal axis of the semiconductor mesa and at least one body zone forming first pn junctions with the source zones and a second pn junction with a drift zone. The semiconductor device further includes stripe-shaped electrode structures on opposite sides of the semiconductor mesa and separation regions between neighboring ones of the source zones. At least one of the electrode structures includes a gate electrode. In the separation regions, at least one of (i) a capacitive coupling between the gate electrode and the semiconductor mesa and (ii) a conductivity of majority charge carriers of the drift zone is lower than outside of the separation regions.

Abstract: According to an embodiment of a semiconductor device, the device includes first and second trenches formed in a semiconductor body and an electrode disposed in each of the trenches. One of the electrodes is a gate electrode, and the other electrode is electrically disconnected from the gate electrode. The semiconductor device further includes a semiconductor mesa between the trenches. The semiconductor mesa includes a separation region and at least one of a source region and a body region located in the semiconductor mesa. A drift zone is provided below the at least one of the source region and the body region. In the separation region, at least one of (i) a capacitive coupling between the gate electrode and the semiconductor mesa and (ii) a conductivity of majority charge carriers of the drift zone is lower than outside of the separation region.

Abstract: A semiconductor device includes a semiconductor mesa having source zones and at least one body zone forming first pn junctions with the source zones and a second pn junction with a drift zone. Electrode structures are provided on opposite sides of the semiconductor mesa, at least one of the electrode structures having a gate electrode configured to control a charge carrier flow through the at least one body zone. A separation region is arranged along an extension direction of the semiconductor mesa. In the separation region, the semiconductor mesa has a constricted portion that is partially or completely oxidized. Additional semiconductor device embodiments are described.

Abstract: According to an embodiment of a semiconductor device, the device includes first and second trenches formed in a semiconductor body and an electrode disposed in each of the trenches. One of the electrodes is a gate electrode, and the other electrode is electrically disconnected from the gate electrode. The semiconductor device further includes a semiconductor mesa between the trenches. The semiconductor mesa includes a separation region and at least one of a source region and a body region located in the semiconductor mesa. A drift zone is provided below the at least one of the source region and the body region. In the separation region, at least one of (i) a capacitive coupling between the gate electrode and the semiconductor mesa and (ii) a conductivity of majority charge carriers of the drift zone is lower than outside of the separation region.

Abstract: A semiconductor device includes a semiconductor mesa having source zones and at least one body zone forming first pn junctions with the source zones and a second pn junction with a drift zone. Electrode structures are provided on opposite sides of the semiconductor mesa, at least one of the electrode structures having a gate electrode configured to control a charge carrier flow through the at least one body zone. A separation region is arranged along an extension direction of the semiconductor mesa. In the separation region, the semiconductor mesa has a constricted portion that is partially or completely oxidized. Additional semiconductor device embodiments are described.

Abstract: A semiconductor device includes transistor cells and control structures. The transistor cells include source zones of a first conductivity type and body zones of a second conductivity type. The source and body zones are formed in a semiconductor mesa formed from a portion of a semiconductor body. The control structures include first portions extending from a first surface into the semiconductor body on at least two opposing sides of the semiconductor mesa, second portions between the first portions and separated from the first surface by portions of the semiconductor mesa, and third portions connecting the first and the second portions and separated from the first surface by portions of the semiconductor mesa. Constricted sections of the semiconductor mesa separate third portions neighboring each other along a horizontal longitudinal extension of the semiconductor mesa.

Abstract: A semiconductor device includes a semiconductor mesa having source zones separated from each other along a longitudinal axis of the semiconductor mesa and at least one body zone forming first pn junctions with the source zones and a second pn junction with a drift zone. Electrode structures are on opposite sides of the semiconductor mesa, at least one of which includes a gate electrode configured to control a charge carrier flow through the at least one body zone. First portions of the at least one body zone are formed between the source zones and separation regions. In the separation regions, at least one of (i) a capacitive coupling between the gate electrode and the semiconductor mesa and (ii) a conductivity of majority charge carriers of the drift zone is lower than outside of the separation region.

Abstract: A method of manufacturing a semiconductor device includes forming electrode trenches in a semiconductor substrate between semiconductor mesas that separate the electrode trenches, the semiconductor mesas including portions of a drift layer of a first conductivity type and a body layer of a second, complementary conductivity type between a first surface of the semiconductor substrate and the drift layer, respectively. The method further includes forming isolated source zones of the first conductivity type in the semiconductor mesas, the source zones extending from the first surface into the body layer. The method also includes forming separation structures in the semiconductor mesas between neighboring source zones arranged along an extension direction of the semiconductor mesas, the separation structures forming partial or complete constrictions of the semiconductor mesa, respectively.

Abstract: A semiconductor device includes a body zone in a semiconductor mesa, which is formed between neighboring control structures that extend from a first surface into a semiconductor body. A drift zone forms a first pn junction with the body zone. In the semiconductor mesa, the drift zone includes a first drift zone section that includes a constricted section of the semiconductor mesa. A minimum horizontal width of the constricted section parallel to the first surface is smaller than a maximum horizontal width of the body zone. An emitter layer between the drift zone and the second surface parallel to the first surface includes at least one first zone of a conductivity type of the drift zone.

Abstract: A method of manufacturing a semiconductor device includes forming electrode trenches in a semiconductor substrate between semiconductor mesas that separate the electrode trenches, the semiconductor mesas including portions of a drift layer of a first conductivity type and a body layer of a second, complementary conductivity type between a first surface of the semiconductor substrate and the drift layer, respectively. The method further includes forming isolated source zones of the first conductivity type in the semiconductor mesas, the source zones extending from the first surface into the body layer. The method also includes forming separation structures in the semiconductor mesas between neighboring source zones arranged along an extension direction of the semiconductor mesas, the separation structures forming partial or complete constrictions of the semiconductor mesa, respectively.

Abstract: A semiconductor device includes transistor cells and control structures. The transistor cells include source zones of a first conductivity type and body zones of a second conductivity type. The source and body zones are formed in a semiconductor mesa formed from a portion of a semiconductor body. The control structures include first portions extending from a first surface into the semiconductor body on at least two opposing sides of the semiconductor mesa, second portions between the first portions and separated from the first surface by portions of the semiconductor mesa, and third portions connecting the first and the second portions and separated from the first surface by portions of the semiconductor mesa. Constricted sections of the semiconductor mesa separate third portions neighboring each other along a horizontal longitudinal extension of the semiconductor mesa.

Abstract: A semiconductor device includes a semiconductor mesa that includes at least one body zone forming first pn junctions with source zones and a second pn junction with a drift zone. Electrode structures are on opposite sides of the semiconductor mesa. At least one of the electrode structures includes a gate electrode configured to control a charge carrier flow through the at least one body zone. In a separation region between the source zones, which are arranged along an extension direction of the semiconductor mesa, the semiconductor mesa includes at least one partial or complete constriction.

Abstract: A semiconductor device includes transistor cells with source zones of a first conductivity type and body zones of a second conductivity type. The source and body zones are formed in a semiconductor mesa formed from a portion of a semiconductor body. Control structures include first portions extending into the semiconductor body on at least two opposing sides of the semiconductor mesa, second portions in a distance to the first surface between the first portions, and third portions in a distance to the first surface and connecting the first and the second portions, wherein constricted sections of the semiconductor mesa are formed between neighboring third portions.

Abstract: A semiconductor device includes a semiconductor mesa having source zones separated from each other along a longitudinal axis of the semiconductor mesa and at least one body zone forming first pn junctions with the source zones and a second pn junction with a drift zone. Electrode structures are on opposite sides of the semiconductor mesa, at least one of which includes a gate electrode configured to control a charge carrier flow through the at least one body zone. First portions of the at least one body zone are formed between the source zones and separation regions. In the separation regions, at least one of (i) a capacitive coupling between the gate electrode and the semiconductor mesa and (ii) a conductivity of majority charge carriers of the drift zone is lower than outside of the separation region.