Abstract: A method, an apparatus, and a computer program are provided for reducing power consumption and area of a memory subsystem. In many typical memory subsystems, dynamic topologies are employed to detect logic levels in memory; however, dynamic topologies often require clocking. Both power and area are consumed as a result of the clocking. To combat the consumption of power and area, the memory subsystem has been modified so that an enable signal, that must be present, is utilized instead to provide the clocking.

Abstract: Disclosed is an electronic chip containing a plurality of electronic circuit partitions, distributed over the area of the chip, each including a processor core and a clock phase domain different from cores in other partitions of the chip. A source of same frequency, but different phase clock signals representing different clock domains, provides different phase signals to adjacent partitions for the purpose of reducing instantaneous magnitude switching currents. Intra-chip communication circuitry distributes control and data signals between partitions.

Abstract: The present invention provides a system for mitigating impulse noise effects in a digital data transmission system, particularly in a DSL-based communications system (300), by optimizing error correction systems with an erasure forecasting scheme. Within the communications system, encoding and structuring constructs form and permute data transmission units for transmission in a deterministic manner (i.e., having known, fixed characteristics). Once data transmission units have been received over a transmission channel, de-structuring and decoding constructs inversely permute and decode those data transmission units, according to the deterministic manner. Data decoding is monitored (302), and the occurrence of an impulse noise event in the transmission channel is identified (304). A first data transmission unit affected by the impulse noise event is decoded (306).

Abstract: A system and method are provided for efficiently processing data with a cache in a computer system. The computer system has a processor, a cache and a system memory. The processor issues a data request for streaming data. The streaming data has one or more small data portions. The system memory is in communication with the processor. The system memory has a specific area for storing the streaming data. The cache is coupled to the processor. The cache has a predefined area locked for the streaming data. A cache controller is coupled to the cache and is in communication with both the processor and the system memory to transmit at least one small data portion of the streaming data from the specific area of the system memory to the predefined area of the cache when the one small data portion is not found in the predefined area of the cache.

Abstract: The present invention provides for determining an MRU or LRU way of a partitioned cache. The partitioned cache has a plurality of ways. There are a plurality of partitions, each partition comprising at least one way. An updater is employable to update a logic table as a function of an access of a way. Partition comparison logic is employable to determine whether two ways are members of the same partition, and to allow the comparison of the ways correlating to a first matrix indices and a second matrix indices. An intersection generator is employable to create an intersection box of the memory table as a function of a first and second matrix indices. Access order logic is employable to combine the output of the intersection generator, thereby determining which way is the most or least recently used way.

Abstract: An electronic device having an adapter. The electronic device comprises a first circuit board, a first electronic element disposed on the first circuit board, a first adapter having a first surface, a second surface and a recess, and a second circuit board. The first adapter is electrically connected to the first and second circuit boards and disposed therebetween, the first electronic element is accommodated in the recess.

Abstract: The invention provides an apparatus and method for the active alignment and coupling of separate optical components consisting of a light-emitting component and a light-receiving component. It comprises first alignment means having a relatively lower optical resolving power stage that is adapted to perform coarse alignment of the light-emitting component to locate an approximate location of its point of highest intensity, and second alignment means having a relatively higher optical resolving power stage that is adapted to perform fine alignment of the light-emitting component to locate a more precise location of the said point of highest intensity. Accordingly, coarse alignment may be performed using a multi-mode fiber and fine alignment may be performed using a single-mode fiber that may further be coupled to the light-emitting component.

Abstract: The present invention provides for asynchronous DMA command completion notification in a computer system. A command tag, associated with a plurality DMA command is generated. A DMA data movement command having the command tag is grouped with another DMA data movement command having the command tag. DMA commands belonging to the same tag group are monitored to see whether all DMA commands of the same tag group are completed.

Abstract: The present invention provides for atomic update primitives in an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfers. At least one lock line command is generated from a set comprising a get lock line command with reservation, a put lock line conditional command, and a put lock line unconditional command.

Abstract: A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor. The first processor is in need of data. The system also includes a directory in communication with the first processor. The directory receives a data request for the data and contains information as to where the data is stored. A cache is coupled to the second processor. An internal bus is coupled between the first processor and the cache to transfer the data from the cache to the first processor when the data is found to be stored in the cache.

Abstract: The invention provides an apparatus and method for the active alignment and coupling of separate optical components consisting of a light-emitting component and a light-receiving component. It comprises first alignment means having a relatively lower optical resolving power stage that is adapted to perform coarse alignment of the light-emitting component to locate an approximate location of its point of highest intensity, and second alignment means having a relatively higher optical resolving power stage that is adapted to perform fine alignment of the light-emitting component to locate a more precise location of the said point of highest intensity. Accordingly, coarse alignment may be performed using a multi-mode fiber and fine alignment may be performed using a single-mode fiber that may further be coupled to the light-emitting component.

Abstract: A system and method are provided for efficiently processing data with a cache in a computer system. The computer system has a processor, a cache and a system memory. The processor issues a data request for streaming data. The streaming data has one or more small data portions. The system memory is in communication with the processor. The system memory has a specific area for storing the streaming data. The cache is coupled to the processor. The cache has a predefined area locked for the streaming data. A cache controller is coupled to the cache and is in communication with both the processor and the system memory to transmit at least one small data portion of the streaming data from the specific area of the system memory to the predefined area of the cache when the one small data portion is not found in the predefined area of the cache.

Abstract: The present invention provides for determining an MRU or LRU way of a partitioned cache. The partitioned cache has a plurality of ways. There are a plurality of partitions, each partition comprising at least one way. An updater is employable to update a logic table as a function of an access of a way. Partition comparison logic is employable to determine whether two ways are members of the same partition, and to allow the comparison of the ways correlating to a first matrix indices and a second matrix indices. An intersection generator is employable to create an intersection box of the memory table as a function of a first and second matrix indices. Access order logic is employable to combine the output of the intersection generator, thereby determining which way is the most or least recently used way.

Abstract: This invention concerns particulate reinforced Al-based composites, and the near net shape forming process of their components. The average size of the reinforced particle in the invented composites is 0.1˜3.5 &mgr;m and the volume percentage is 10˜40%, and a good interfacial bonding between the reinforced particulate and the matrix is formed with the reinforced particles uniformly distributed. The production method of its billet is to have the reinforced particles and Al-base alloy powder receive variable-speed high-energy ball-milling in the balling drum. Then, with addition of a liquid surfactant, the ball-mill proceeds to carry on ball-milling. After the ball-milling, the produced composite powder undergoes cold isostatic pressing and the subsequent vacuum sintering or vacuum hot-pressing to be shaped into a hot compressed billet, which in turn undergoes semisolid thixotropic forming and may be shaped into complex-shaped components. These components can be used in various fields.

Abstract: A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor. The first processor is in need of data. The system also includes a directory in communication with the first processor. The directory receives a data request for the data and contains information as to where the data is stored. A cache is coupled to the second processor. An internal bus is coupled between the first processor and the cache to transfer the data from the cache to the first processor when the data is found to be stored in the cache.

Abstract: The present invention provides a data access ring. The data access ring has a plurality of attached processor units (APUs) and a local store associated with each APU. The data access ring has a data command ring, coupled to the plurality of APUs. The data command ring is employable to carry indicia of a selection of one of the plurality of APUs to the APUs. The data access ring also has a data address ring, coupled to the plurality of APUs. The data address ring is further employable to carry indicia of a memory location to the selected APU a predetermined number of clock cycles after the data command ring carries the indicia of the selection of one of the plurality of APUs. The data access ring also has a data transfer ring, coupled to the plurality of APUs. The data transfer ring is employable to transfer data to or from the memory location associated with the APU a predetermined number of clock cycles after the data address ring carries the indicia of the memory location to the selected APU.

Abstract: Disclosed is an electronic chip containing a plurality of electronic circuit partitions, distributed over the area of the chip, each including a processor core and a clock phase domain different from cores in other partitions of the chip. A source of same frequency, but different phase clock signals representing different clock domains, provides different phase signals to adjacent partitions for the purpose of reducing instantaneous magnitude switching currents. Intra-chip communication circuitry distributes control and data signals between partitions.

Abstract: A sync server responds to messages from a client to synchronize data between a client dataset and a reference dataset. Various messages may be received from the client, including changes to the client dataset, requests for confirmation of received changes, or requests for changes to the reference dataset. When the server receives client changes, the server reads record ID's from the messages, writes the ID's into a change ID list, and places the changes into a queue for processing. When the server receives a request for confirmation of changes, the server uses the change ID list to confirm receipt of changes, including changes that have not yet been processed. If the server receives a message that requires that the reference dataset be up-to-date, such as a request for changes from the reference dataset, the sync server processes all of the changes in the queue before processing the new message.

Abstract: This invention relates to enzymatic removal of type A and B antigens from blood group A, B, and AB reactive cells in blood products, and thereby converting these to non-A and non-B reactive cells. The invention further relates to using unique &agr;N-acetylgalactosamimidases and &agr;-galactosidases with superior kinetic properties for removing the immunodominant monosaccharides of the blood group A and B antigens and improved performance in enzymatic conversion of red blood cells.

Abstract: A back lighting source module for a liquid crystal display comprises a pulse width modulation (PWM) controller for providing a pulse width signal to control output current of a lighting element. A half bridge converter includes two power transistors connected in series. An output is formed in a middle between the two power transistors. The output is controllable by the signal from the PWM controller to perform alternating opening and closing. A resonance circuit generates a sine-wave voltage to empower the lighting element. A feedback circuit includes a resistor. When a load varies, a voltage signal generated between two ends of the resistor of the feedback circuit timely changes a conductive time of the power transistors of the half bridge converter to complete regulation of current passing through the lighting element.