Abstract: A method for forming features in dielectric layers and opening barrier layers for a plurality of wafers and cleaning an etch chamber after processing and removing each wafer of the plurality of wafers is provided. A wafer of the plurality of wafers is placed into the etch chamber wherein the wafer has a barrier layer over the wafer and a dielectric layer over the barrier layer. The dielectric layer is etched. The barrier layer is opened. The wafer is removed from the etch chamber. A waferless automatic cleaning of the etch chamber without the wafer is provided. The waferless automatic cleaning comprises providing a waferless automatic cleaning gas comprising oxygen and nitrogen to the etch chamber and forming a waferless automatic cleaning plasma from the waferless automatic cleaning gas to clean the etch chamber.

Abstract: An apparatus for providing different gases to different zones of a processing chamber is provided. A gas supply for providing an etching gas flow is provided. A flow splitter in fluid connection with the gas supply for splitting the etching gas flow from the gas supply into a plurality of legs is provided. A tuning gas system in fluid connection to at least one of the legs of the plurality of legs is provided.

Abstract: A semiconductor chip formed on a substrate is provided. An oxygen-doped silicon carbide etch stop layer is formed over the substrate. An organosilicate glass layer is formed over the oxygen-doped silicon carbide etch stop layer. A feature is selectively etched in the organosilicate glass layer using an etch with an organosilicate glass to oxygen-doped silicon carbide selectivity greater than 5:1.

Abstract: A method of forming a semiconductor device is provided. A wafer with a dielectric layer disposed under a photoresist mask is placed in an etch chamber. The dielectric layer is etched. The wafer is raised. A cleaning gas is provided. A plasma is formed from the cleaning gas. A polymer that has formed on the bevel of the wafer is removed using the plasma from the cleaning gas. The wafer is removed from the etch chamber.

Abstract: A method for etching a trench to a trench depth in a dielectric layer over a substrate is provided. An ARC is applied over the dielectric layer. A photoresist mask is formed on the ARC, where the photoresist mask has a thickness. The ARC is etched through. A trench is etched into the dielectric layer with a dielectric to photoresist etch selectivity between 1:1 and 2:1.

Abstract: A method for forming features in dielectric layers and opening barrier layers for a plurality of wafers and cleaning an etch chamber after processing and removing each wafer of the plurality of wafers is provided. A wafer of the plurality of wafers is placed into the etch chamber wherein the wafer has a barrier layer over the wafer and a dielectric layer over the barrier layer. The dielectric layer is etched. The barrier layer is opened. The wafer is removed from the etch chamber. A waferless automatic cleaning of the etch chamber without the wafer is provided. The waferless automatic cleaning comprises providing a waferless automatic cleaning gas comprising oxygen and nitrogen to the etch chamber and forming a waferless automatic cleaning plasma from the waferless automatic cleaning gas to clean the etch chamber.

Abstract: A method for etching a trench to a trench depth in a dielectric layer over a substrate is provided. An ARC is applied over the dielectric layer. A photoresist mask is formed on the ARC, where the photoresist mask has a thickness. The ARC is etched through. A trench is etched into the dielectric layer with a dielectric to photoresist etch selectivity between 1:1 and 2:1.

Abstract: A method of etching a substrate in a plasma processing system is disclosed. The substrate has a semi-conductor layer, a first barrier layer disposed above the semi-conductor layer, a low-k layer disposed above the first barrier layer, a third hard mask layer disposed above the low-k layer; a second hard mask layer disposed above the third hard mask layer, and a first hard mask layer disposed above the second hard mask layer.

Abstract: A temperature-controlled hot edge ring assembly adapted to surround a substrate support in a plasma reaction chamber. The assembly includes a conductive lower ring, a ceramic intermediate ring, and an upper ring. The intermediate ring overlies the lower ring and is adapted to be attached via the lower ring to an RF electrode. The upper ring overlies the intermediate ring, and has an upper surface exposed to an interior of a plasma reaction chamber.

Abstract: A method for etching a trench to a trench depth in a dielectric layer over a substrate is provided. An ARC is applied over the dielectric layer. A photoresist mask is formed on the ARC, where the photoresist mask has a thickness. The ARC is etched through. A trench is etched into the dielectric layer with a dielectric to photoresist etch selectivity between 1:1 and 2:1.

Abstract: A plasma in a vacuum chamber where a workpiece is processed is bounded by a plasma confinement volume including a region between a first electrode simultaneously responsive to power at first and second RF frequencies and a DC grounded second electrode. A DC grounded extension is substantially aligned with the first electrode. A substantial percentage of power at the first frequency is coupled to a path including the first and second electrodes but not the extension while a substantial percentage of power at the second frequency is coupled to a path including the first electrodes and extension, but not the second electrode. Changing the relative powers at the first and second frequencies, as applied to the first electrode, controls DC bias voltage of the first electrode.

Abstract: The temperature of a plasma chamber of a semiconductor fabrication tool is maintained substantially constant utilizing a variety of techniques, separately or in combination. One technique is to provide the exterior surface of the plasma chamber dome with a plurality of fins projecting into high velocity regions of an overlying airflow in order to dissipate heat from the chamber. Ducting defined by cover overlying the exposed exterior surface of the dome may also feature projecting lips or an airfoil to place high velocity components of the airflow into contact within the exterior dome surface and the fins. Other techniques include employing a high speed fan to control airflow circulation, and the use of temperature sensors in communication the fan through a processor to control fan speed and thereby regulate chamber temperature.

Abstract: An apparatus for providing a plasma etch of a layer over a wafer is provided. A capacitively coupled process chamber is provided. A gas source is provided. A first and a second electrode are provided within the process chamber. A first radio frequency power source is electrically connected to at least one of the first and second electrodes, where the first radio frequency power source provides radio frequency power. A second radio frequency power source is electrically connected to at least one of the first and second electrodes. A first modulation control is connected to the first radio frequency power source, to provide a controlled modulation of the first radio frequency power source.

Abstract: A method for etching a feature in a low-k dielectric layer through a photoresist etch mask over a substrate. A gas-modulated cyclic stripping process is performed for more than three cycles for stripping a single photoresist mask. Each cycle of the gas-modulated cyclic stripping process comprises performing a protective layer formation phase and a stripping phase. The protective layer forming phase using first gas chemistry with a deposition gas chemistry, wherein the protective layer forming phase is performed in about 0.005 to 10 seconds for each cycle. The performing the stripping phase for stripping the photoresist mask using a second gas chemistry using a stripping gas chemistry, where the first gas chemistry is different than the second gas chemistry, wherein the etching phase is performed in about 0.005 to 10 seconds for each cycle.

Abstract: A semiconductor chip formed on a substrate is provided. An oxygen-doped silicon carbide etch stop layer is formed over the substrate. An organosilicate glass layer is formed over the oxygen-doped silicon carbide etch stop layer. A feature is selectively etched in the organosilicate glass layer using an etch with an organosilicate glass to oxygen-doped silicon carbide selectivity greater than 5:1.

Abstract: An apparatus for providing different gases to different zones of a processing chamber is provided. A gas supply for providing an etching gas flow is provided. A flow splitter in fluid connection with the gas supply for splitting the etching gas flow from the gas supply into a plurality of legs is provided. A tuning gas system in fluid connection to at least one of the legs of the plurality of legs is provided.

Abstract: Etching a layer over a substrate is provided. The substrate is placed in a plasma processing chamber. A first gas is provided to an inner zone within the plasma processing chamber. A second gas is provided to the outer zone within the plasma processing chamber, where the outer zone surrounds the inner zone and the first gas is different than the second gas. Plasmas are simultaneously generated from the first gas and second gas. The layer is etched, where the layer is etched by the plasmas from the first gas and second gas.

Abstract: An apparatus for providing a gas from a gas supply to at least two different zones in a process chamber is provided. A flow divider provides a fluid connection to the gas supply, where the flow divider splits gas flow from the gas supply into a plurality of legs. A master leg is in fluid connection with the flow divider, where the master leg comprises a master fixed orifice. A first slave leg is in fluid connection with the flow divider and in parallel with the master leg, where the first slave leg comprises a first slave leg valve and a first slave leg fixed orifice.

Abstract: The present invention includes a system and method for confining plasma within a plasma processing chamber. The plasma processing apparatus comprises a first electrode, a power generator, a second electrode, at least one confinement ring, and a ground extension surrounding the first electrode. The first electrode is configured to receive a workpiece and has an associated first electrode area. The power generator is operatively coupled to the first electrode, and the power generator is configured to generate RF power that is communicated to the first electrode. The second electrode is disposed at a distance from the first electrode. The second electrode is configured to provide a complete electrical circuit for RF power communicated from the first electrode. Additionally, the second electrode has a second electrode area that is greater than the first electrode area. At least one confinement ring is configured to assist confine the plasma.

Abstract: An improved upper electrode system has a multi-part electrode in which a central portion of the electrode having high wear is replaceable independent of an outer peripheral portion of the electrode. The upper electrode can be used in plasma processing systems for processing semiconductor substrates, such as by etching or CVD. The multi-part upper electrode system is particularly useful for large size wafer processing chambers, such as 300 mm wafer processing chambers for which monolithic electrodes are unavailable or costly.