Patents by Inventor Peter Logan

Peter Logan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9984766
    Abstract: A data processing apparatus includes a memory and memory protection circuitry for providing an operational path to the memory during operational use of the memory. A memory built-in self-test controller 34 performs built-in self-test operations upon the memory using either an indirect test access path to the memory via the memory protection circuitry or a direct test access path to the memory which bypasses the memory protection circuitry. Thus, the correct operation of the memory protection circuitry itself can be tested in addition to the correct operation of the memory.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: May 29, 2018
    Assignee: ARM Limited
    Inventors: Alan Jeremy Becker, Peter Logan Harrod
  • Patent number: 8260831
    Abstract: A system and method for implementing storage management with threshold control is provided. A flexible storage manager associates storage devices having a similar performance characteristic into logical constructs called storage groups. Storage groups having the same performance characteristic from a plurality of storage systems are organized into storage pools. The flexible storage manager automatically provisions storage on a storage pool basis. Should a low threshold utilization be exceeded, the flexible storage manager performs a set of management policies to lower the utilization of a storage pool to the low threshold.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: September 4, 2012
    Assignee: NetApp, Inc.
    Inventors: John Charles Tyrrell, Konstantinos Roussos, Peter Logan Smoot
  • Patent number: 8250351
    Abstract: Reset control circuitry is disclosed, for controlling a first reset signal for resetting at least a first portion of a circuit and a further reset signal for resetting at least a second portion of said circuit, said reset control circuitry comprising: an input for receiving an input first reset signal; an input for receiving an input further reset signal; an output for outputting an output first reset signal; and an output for outputting an output further reset signal; said reset control circuitry being responsive to detecting deassertion of said input first reset signal when said input further reset signal is asserted to delay deassertion of said output first reset signal so that said output first reset signal is deasserted at a same time or later than said input further reset signal.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: August 21, 2012
    Assignee: ARM Limited
    Inventors: David Michael Gilday, Peter Logan Harrod
  • Patent number: 7949914
    Abstract: A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: May 24, 2011
    Assignee: ARM Limited
    Inventors: Peter Logan Harrod, Edmond John Simon Ashfield, Thomas Sean Houlihane, Paul Kimelman, Simon John Craske, Michael John Williams
  • Publication number: 20100223518
    Abstract: A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.
    Type: Application
    Filed: January 29, 2010
    Publication date: September 2, 2010
    Inventors: Peter Logan Harrod, Edmond John Simon Ashfield, Thomas Sean Houlihane, Paul Kimelman, Simon John Craske, Michael John Williams
  • Patent number: 7743294
    Abstract: A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.
    Type: Grant
    Filed: November 20, 2006
    Date of Patent: June 22, 2010
    Assignee: ARM Limited
    Inventors: Peter Logan Harrod, Edmond John Simon Ashfield, Thomas Sean Houlihane, Paul Kimelman, Simon John Craske, Michael John Williams
  • Publication number: 20100138640
    Abstract: Reset control circuitry is disclosed, for controlling a first reset signal for resetting at least a first portion of a circuit and a further reset signal for resetting at least a second portion of said circuit, said reset control circuitry comprising: an input for receiving an input first reset signal; an input for receiving an input further reset signal; an output for outputting an output first reset signal; and an output for outputting an output further reset signal; said reset control circuitry being responsive to detecting deassertion of said input first reset signal when said input further reset signal is asserted to delay deassertion of said output first reset signal so that said output first reset signal is deasserted at a same time or later than said input further reset signal.
    Type: Application
    Filed: December 2, 2008
    Publication date: June 3, 2010
    Applicant: ARM LIMITED
    Inventors: David Michael Gilday, Peter Logan Harrod
  • Publication number: 20080272231
    Abstract: A winged device has an axial support which is mounted for reciprocating rotary motion about a longitudinal axis of the support. A first wing vane is mounted to the axial support for rotation with the axial support. A second wing vane is mounted to the axial support. A cam follower is constrained to a defined movement path by a cam. A first connector connects the first wing vane to the cam follower such that the cam follower is moved along the cam by the first connector as the first wing vane moves with rotation of the axial support about its longitudinal axis. A second connector connects the second wing vane to the cam follower such that the second wing vane is moved by the second connector as the cam follower member is moved along the cam. The cam profile is defined relative to the axis of the axial support such that the relative orientation of the wing vanes changes as the axial support is rotated.
    Type: Application
    Filed: December 5, 2006
    Publication date: November 6, 2008
    Inventor: Peter Logan Sinclair
  • Patent number: 7373550
    Abstract: Software built in self test computer programs 12 are generated using a genetic algorithm 14 technique. A fault simulator 20 is used to simulate candidate software built in self test computer programs and compare the simulated execution, such to deliberately introduced test faults, with expected execution outcomes previously derived for that candidate program to determine the sensitivity of that candidate program to the faults which are introduced. This score can be fed back into the genetic algorithm mutation to converge the mutation process upon appropriately fault sensitive software built in self test program code.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: May 13, 2008
    Assignee: ARM Limited
    Inventors: Jonathan William Brawn, Simon John Craske, Peter Logan Harrod, Eric Jason Furbish
  • Publication number: 20070167785
    Abstract: A system is described having a JTAG diagnostic unit 2 and a serial wire diagnostic unit 4. A watcher unit 6 is connected to a data connection 14 shared between the diagnostic units 2, 4. Special patterns detected upon the shared data connection 14 serve to switch between diagnostic modes with respective ones of the diagnostic units 2, 4 becoming active.
    Type: Application
    Filed: November 20, 2006
    Publication date: July 19, 2007
    Applicant: ARM Limited
    Inventors: Peter Logan Harrod, Edmond John Simon Ashfield, Thomas Sean Houlihane, Paul Kimelman, Simon John Craske, Michael John Williams
  • Patent number: 7204455
    Abstract: A drive assembly for use with a mechanical flying or walking device comprises an articulated member (7) having first and second portions (7a, 7b) arranged such that the portions move relative to each other, and a drive mechanism (9) for imparting motion to the articulated member. The drive mechanism (9) comprises: a drive member for imparting a cyclic motion on the articulated member, and a control member for controlling, in a predetermined manner, the relative position of the first and second portions during each cycle of the cyclic motion of the articulated member. In the case of a mechanical flying device, two such drive assemblies may be provided, the articulated member of each assembly forming a wing.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: April 17, 2007
    Inventor: Peter Logan Sinclair
  • Patent number: 7085978
    Abstract: Testing of the test signal connections to a functional block of circuitry within an integrated circuit is made using wrapper serial scan chain cells of a wrapper serial scan chain. These wrapper cells can then be used to validate that the correct signals are reaching test signal inputs and the correct signals are reaching their destination from test signal outputs when that functional block of circuitry is incorporated within a larger design, e.g., a system-on-chip design.
    Type: Grant
    Filed: September 17, 2002
    Date of Patent: August 1, 2006
    Assignee: ARM Limited
    Inventors: Teresa Louise McLaurin, Peter Logan Harrod, Raul Armando Garibay
  • Publication number: 20060124541
    Abstract: A process for treatment of waste activated sludge from a BNR process, which includes the steps of: (a) concentration of the activated sludge from a total solids content (dry weight) of 0.1-1.0% w/v to an increased solids content of 1.5-5.0% w/v, wherein said solids largely contain bacterial biomass from prior aeration of the activated sludge; (b) disrupting bacterial cells contained in the biomass so as to release fermentable nutrients from said bacterial cells; (c) passing the activated sludge from step (b) through an anaerobic digester system; and (d) removing N and/or P from the residue obtained after step (c).
    Type: Application
    Filed: September 30, 2002
    Publication date: June 15, 2006
    Applicant: Fungi-Gulp Pty LTD
    Inventors: Peter Logan, Ian Jones
  • Publication number: 20040195436
    Abstract: A drive assembly for use with a mechanical flying or walking device comprises an articulated member (7) having first and second portions (7a, 7b) arranged such that the portions move relative to each other, and a drive mechanism (9) for imparting motion to the articulated member. The drive mechanism (9) comprises: a drive member for imparting a cyclic motion on the articulated member, and a control member for controlling, in a predetermined manner, the relative position of the first and second portions during each cycle of the cyclic motion of the articulated member. In the case of a mechanical flying device, two such drive assemblies may be provided, the articulated member of each assembly forming a wing.
    Type: Application
    Filed: December 23, 2003
    Publication date: October 7, 2004
    Inventor: Peter Logan Sinclair
  • Publication number: 20040054948
    Abstract: Testing of the test signal connections to a functional block of circuitry within an integrated circuit is made using wrapper serial scan chain cells of a wrapper serial scan chain such that it may be validated that the correct signals are reaching test signal inputs and the correct signals are reaching their destination from test signal outputs when that functional block of circuitry is incorporated within a larger design, such as a system-on-chip design.
    Type: Application
    Filed: September 17, 2002
    Publication date: March 18, 2004
    Applicant: ARM LIMITED
    Inventors: Teresa Louise McLaurin, Peter Logan Harrod, Raul Armando Garibay
  • Patent number: 6052774
    Abstract: The present invention provides a debugger interface unit for a data processing apparatus, comprising a control register having a number of fields, each field corresponding to a particular exception routine, and each field being settable to indicate that the debugger wishes to identify an access to the corresponding exception routine. Further, an exception routine catch logic is provided to receive a first signal when a processor core within the data processing apparatus issues an instruction fetch command for an exception routine, and to determine from an instruction address issued with the instruction fetch command which exception routine is being fetched. In addition, the catch logic is arranged to reference the field of the control register corresponding to the determined exception routine to determine if that field has been set, and if the field has been set, to output a breakpoint signal to the processor core.
    Type: Grant
    Filed: March 6, 1998
    Date of Patent: April 18, 2000
    Assignee: ARM Limited
    Inventors: Simon Anthony Segars, Peter Logan Harrod, Andrew John Merritt