Abstract: A data processing apparatus includes a memory and memory protection circuitry for providing an operational path to the memory during operational use of the memory. A memory built-in self-test controller 34 performs built-in self-test operations upon the memory using either an indirect test access path to the memory via the memory protection circuitry or a direct test access path to the memory which bypasses the memory protection circuitry. Thus, the correct operation of the memory protection circuitry itself can be tested in addition to the correct operation of the memory.

Abstract: Reset control circuitry is disclosed, for controlling a first reset signal for resetting at least a first portion of a circuit and a further reset signal for resetting at least a second portion of said circuit, said reset control circuitry comprising: an input for receiving an input first reset signal; an input for receiving an input further reset signal; an output for outputting an output first reset signal; and an output for outputting an output further reset signal; said reset control circuitry being responsive to detecting deassertion of said input first reset signal when said input further reset signal is asserted to delay deassertion of said output first reset signal so that said output first reset signal is deasserted at a same time or later than said input further reset signal.

Abstract: A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.

Abstract: A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.

Abstract: A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic modes with respective ones of the diagnostic units becoming active.

Abstract: Reset control circuitry is disclosed, for controlling a first reset signal for resetting at least a first portion of a circuit and a further reset signal for resetting at least a second portion of said circuit, said reset control circuitry comprising: an input for receiving an input first reset signal; an input for receiving an input further reset signal; an output for outputting an output first reset signal; and an output for outputting an output further reset signal; said reset control circuitry being responsive to detecting deassertion of said input first reset signal when said input further reset signal is asserted to delay deassertion of said output first reset signal so that said output first reset signal is deasserted at a same time or later than said input further reset signal.

Abstract: Software built in self test computer programs 12 are generated using a genetic algorithm 14 technique. A fault simulator 20 is used to simulate candidate software built in self test computer programs and compare the simulated execution, such to deliberately introduced test faults, with expected execution outcomes previously derived for that candidate program to determine the sensitivity of that candidate program to the faults which are introduced. This score can be fed back into the genetic algorithm mutation to converge the mutation process upon appropriately fault sensitive software built in self test program code.

Abstract: A system is described having a JTAG diagnostic unit 2 and a serial wire diagnostic unit 4. A watcher unit 6 is connected to a data connection 14 shared between the diagnostic units 2, 4. Special patterns detected upon the shared data connection 14 serve to switch between diagnostic modes with respective ones of the diagnostic units 2, 4 becoming active.

Abstract: Testing of the test signal connections to a functional block of circuitry within an integrated circuit is made using wrapper serial scan chain cells of a wrapper serial scan chain. These wrapper cells can then be used to validate that the correct signals are reaching test signal inputs and the correct signals are reaching their destination from test signal outputs when that functional block of circuitry is incorporated within a larger design, e.g., a system-on-chip design.

Abstract: Testing of the test signal connections to a functional block of circuitry within an integrated circuit is made using wrapper serial scan chain cells of a wrapper serial scan chain such that it may be validated that the correct signals are reaching test signal inputs and the correct signals are reaching their destination from test signal outputs when that functional block of circuitry is incorporated within a larger design, such as a system-on-chip design.

Abstract: The present invention provides a debugger interface unit for a data processing apparatus, comprising a control register having a number of fields, each field corresponding to a particular exception routine, and each field being settable to indicate that the debugger wishes to identify an access to the corresponding exception routine. Further, an exception routine catch logic is provided to receive a first signal when a processor core within the data processing apparatus issues an instruction fetch command for an exception routine, and to determine from an instruction address issued with the instruction fetch command which exception routine is being fetched. In addition, the catch logic is arranged to reference the field of the control register corresponding to the determined exception routine to determine if that field has been set, and if the field has been set, to output a breakpoint signal to the processor core.