Patents by Inventor Peter Losee

Peter Losee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9123798
    Abstract: An insulating gate field effect transistor (IGFET) device includes a semiconductor body and a gate oxide. The semiconductor body includes a first well region doped with a first type of dopant and a second well region that is doped with an oppositely charged second type of dopant and is located within the first well region. The gate oxide includes an outer section and an interior section having different thickness dimensions. The outer section is disposed over the first well region and the second well region of the semiconductor body. The interior section is disposed over a junction gate field effect transistor region of the semiconductor body. The semiconductor body is configured to form a conductive channel through the second well region and the junction gate field effect transistor region when a gate signal is applied to a gate contact disposed on the gate oxide.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: September 1, 2015
    Assignee: General Electric Company
    Inventors: Stephen Daley Arthur, Kevin Sean Matocha, Ramakrishna Rao, Peter Losee, Alexander Viktorovich Bolotnikov
  • Publication number: 20140159141
    Abstract: An insulating gate field effect transistor (IGFET) device includes a semiconductor body and a gate oxide. The semiconductor body includes a first well region doped with a first type of dopant and a second well region that is doped with an oppositely charged second type of dopant and is located within the first well region. The gate oxide includes an outer section and an interior section having different thickness dimensions. The outer section is disposed over the first well region and the second well region of the semiconductor body. The interior section is disposed over a junction gate field effect transistor region of the semiconductor body. The semiconductor body is configured to form a conductive channel through the second well region and the junction gate field effect transistor region when a gate signal is applied to a gate contact disposed on the gate oxide.
    Type: Application
    Filed: December 12, 2012
    Publication date: June 12, 2014
    Applicant: General Electric Company
    Inventors: Stephen Daley Arthur, Kevin Sean Matocha, Ramakrishna Rao, Peter Losee, Alexander Viktorovich Bolotnikov
  • Patent number: 8377756
    Abstract: In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (228) (P type) and two parallel sources (260) (N type) formed within the well. A plurality of source rungs (262) (doped N) connect sources (260) at multiple locations. Regions between two rungs (262) comprise a body (252) (P type). These features are formed on an N-type epitaxial layer (220), which is formed on an N-type substrate (216). A contact (290) extends across and contacts a plurality of source rungs (262) and bodies (252). Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.
    Type: Grant
    Filed: July 26, 2011
    Date of Patent: February 19, 2013
    Assignee: General Electric Company
    Inventors: Stephen Daley Arthur, Kevin Matocha, Peter Sandvik, Zachary Stum, Peter Losee, James McMahon
  • Publication number: 20130026559
    Abstract: In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (228) (P type) and two parallel sources (260) (N type) formed within the well. A plurality of source rungs (262) (doped N) connect sources (260) at multiple locations. Regions between two rungs (262) comprise a body (252) (P type). These features are formed on an N-type epitaxial layer (220), which is formed on an N-type substrate (216). A contact (290) extends across and contacts a plurality of source rungs (262) and bodies (252). Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.
    Type: Application
    Filed: July 26, 2011
    Publication date: January 31, 2013
    Inventors: Stephen Daley Arthur, Kevin Matocha, Peter Sandvik, Zachary Stum, Peter Losee, James McMahon
  • Patent number: 7144797
    Abstract: A semiconductor device includes a graded junction termination extension. A method for fabricating the device includes providing a semiconductor layer having a pn junction, providing a mask layer adjacent to the semiconductor layer, etching the mask layer to form at least two laterally adjacent steps associated with different mask thicknesses and substantially planar step surfaces, and implanting a dopant species through the mask layer into a portion of the semiconductor layer adjacent to the termination of the pn junction. The semiconductor layer is annealed to activate at least a portion of the implanted dopant species to form the graded junction termination extension.
    Type: Grant
    Filed: September 24, 2004
    Date of Patent: December 5, 2006
    Assignee: Rensselaer Polytechnic Institute
    Inventors: Tat-Sing Paul Chow, Peter Losee, Santhosh Balachandran
  • Publication number: 20060068571
    Abstract: A semiconductor device includes a graded junction termination extension. A method for fabricating the device includes providing a semiconductor layer having a pn junction, providing a mask layer adjacent to the semiconductor layer, etching the mask layer to form at least two laterally adjacent steps associated with different mask thicknesses and substantially planar step surfaces, and implanting a dopant species through the mask layer into a portion of the semiconductor layer adjacent to the termination of the pn junction. The semiconductor layer is annealed to activate at least a portion of the implanted dopant species to form the graded junction termination extension.
    Type: Application
    Filed: September 24, 2004
    Publication date: March 30, 2006
    Applicant: Rensselaer Polytechnic Institute
    Inventors: Tat-Sing Chow, Peter Losee, Santhosh Balachandran