Patents by Inventor Peter M. Asbeck

Peter M. Asbeck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12249963
    Abstract: A method for power amplification uses circuitry including a main amplifier and an auxiliary amplifier that are constructed and operate such that an input is applied to the main and auxiliary amplifiers via an input network. At low power levels, the auxiliary amplifier is off and the main amplifier sees a large impedance. At maximum power level, both the auxiliary and main amplifiers operate at full power and there is a constant phase shift between them. While transitioning from low to maximum power, systematic AM-AM and AM-PM variations generated due to the phase shift provided by the input network, bias differences between the main and auxiliary amplifiers, and nature of the output combiner to compensate device related distortions.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: March 11, 2025
    Assignee: The Regents of the University of California
    Inventors: Seyed Bagher Rabet, Peter M. Asbeck
  • Publication number: 20220416726
    Abstract: Adaptive bias networks include small transistors connected to adjust gate bias voltage of one or more transistors of an amplifier or amplifier stage, or in a main or auxiliary path of a compound amplifier such as a Doherty amplifier. The small transistors are sized to avoid additional loading of the input. The adaptive bias circuits of preferred embodiments adjust the gate bias to produce a boost in gate bias voltage of an nFET transistor when the input power is in an upper portion of the amplifier or amplifier stage's input power range, thereby increasing the gain, and reduce gate bias voltage of a pFET transistor in the upper portion of the amplifier's input power range, thereby also increasing the gain. The adaptive bias networks can be implemented with varactors to vary DC voltage across the varactor to change its capacitance and compensate changing input capacitance of the amplifier input FET.
    Type: Application
    Filed: January 11, 2022
    Publication date: December 29, 2022
    Inventors: Peter M. Asbeck, Sravya Alluri, Narek Rostomyan, Seyed Bagher Rabet
  • Publication number: 20220263475
    Abstract: A method for power amplification uses circuitry including a main amplifier and an auxiliary amplifier that are constructed and operate such that an input is applied to the main and auxiliary amplifiers via an input network. At low power levels, the auxiliary amplifier is off and the main amplifier sees a large impedance. At maximum power level, both the auxiliary and main amplifiers operate at full power and there is a constant phase shift between them. While transitioning from low to maximum power, systematic AM-AM and AM-PM variations generated due to the phase shift provided by the input network, bias differences between the main and auxiliary amplifiers, and nature of the output combiner to compensate device related distortions.
    Type: Application
    Filed: July 29, 2020
    Publication date: August 18, 2022
    Inventors: Peter M. Asbeck, Seyed Bagher Rabet
  • Patent number: 8159295
    Abstract: An embodiment of the invention is a method of generating a reduced bandwidth envelope signal VDD(t) for the power supply modulator of an RF amplifier. An envelope signal of an RF amplifier input Venv(t) is low pass filtered. The filtered envelope signal is subtracted from the envelope signal to obtain a difference signal, which is rectified to produce a residue signal. The residue signal is low pass filtered and added back into the filtered envelope signal. An iterative process of the rectifying, low pass filtering the residue signal adding it back is continued until a condition of VDD(t)?Venv(t) is met. Another embodiment provides a method of generating a reduced bandwidth envelope signal VDD(t) for the power supply modulator of an RF amplifier. An envelope signal of an RF amplifier input Venv(t) is low pass filtered. The filtered envelope signal is subtracted from the envelope signal to obtain a difference signal, which is rectified to produce a residue signal.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: April 17, 2012
    Assignee: The Regents of the University of California
    Inventors: Peter M. Asbeck, Donald Kimball, Jinseong Jeong
  • Patent number: 7953174
    Abstract: The invention is directed to digital generation of RF signals. In the digital domain, digital RF signals are converted to the digital signals clocked at a high speed clock that is phase-synchronized with the RF carrier. A band-pass delta-sigma modulator produces a bit stream from the converted digital signals.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: May 31, 2011
    Assignee: The Regents of the University of California
    Inventors: Peter M. Asbeck, Ian Galton
  • Publication number: 20100295613
    Abstract: An embodiment of the invention is a method of generating a reduced bandwidth envelope signal VDD(t) for the power supply modulator of an RF amplifier. An envelope signal of an RF amplifier input Venv(t) is low pass filtered. The filtered envelope signal is subtracted from the envelope signal to obtain a difference signal, which is rectified to produce a residue signal. The residue signal is low pass filtered and added back into the filtered envelope signal. An iterative process of the rectifying, low pass filtering the residue signal adding it back is continued until a condition of VDD(t)?Venv(t) is met. Another embodiment provides a method of generating a reduced bandwidth envelope signal VDD(t) for the power supply modulator of an RF amplifier. An envelope signal of an RF amplifier input Venv(t) is low pass filtered. The filtered envelope signal is subtracted from the envelope signal to obtain a difference signal, which is rectified to produce a residue signal.
    Type: Application
    Filed: May 21, 2010
    Publication date: November 25, 2010
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Peter M. Asbeck, Donald Kimball, Jinseong Jeong
  • Patent number: 7439556
    Abstract: A substrate driven field effect transistor (FET) and a method of forming the same. In one embodiment, the substrate driven FET includes a substrate having a source contact covering a substantial portion of a bottom surface thereof and a lateral channel above the substrate. The substrate driven FET also includes a drain contact above the lateral channel. The substrate driven FET still further includes a source interconnect that connects the lateral channel to the substrate operable to provide a low resistance coupling between the source contact and the lateral channel.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: October 21, 2008
    Assignee: ColdWatt, Inc.
    Inventors: Berinder P. S. Brar, Peter M. Asbeck
  • Patent number: 6674103
    Abstract: An improved HBT of the invention reduces the current blocking effect at the base-collector interface. Nitrogen is incorporated at the base-collector interface in an amount sufficient to reduce the conduction band energy of the collector at the base-collector interface to equal the conduction band energy of the base. In a preferred embodiment, a nitrogen concentration on the order of 2% is used in a thin ˜20 nm layer at the base-collector interface. Preferred embodiment HBTs of the invention include both GaAs HBTs and InP transistors in various layer structures, e.g., single and double heterojunction bipolar transistors and blocked hole bipolar transistors.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: January 6, 2004
    Assignee: The Regents of the University of California
    Inventors: Charles W. Tu, Peter M. Asbeck, Kazuhiro Mochizuki, Rebecca Welty
  • Publication number: 20030210746
    Abstract: The invention is directed to digital generation of RF signals. In the digital domain, digital RF signals are converted to the digital signals clocked at a high speed clock that is phase-synchronized with the RF carrier. A band-pass delta-sigma modulator produces a bit stream from the converted digital signals.
    Type: Application
    Filed: March 19, 2003
    Publication date: November 13, 2003
    Applicant: The Regents of the University of California
    Inventors: Peter M. Asbeck, Ian Galton
  • Patent number: 6624452
    Abstract: A GaN-based HFET includes a set of layers all having a common face polarity, i.e., all being either Ga-face or N-face. One of the layers is a thin barrier layer having a first face with a positive charge and a second face with a negative charge thereby causing a potential change to occur between the two faces. The if potential change causes the barrier layer to prevent electron flow from a channel layer into a buffer layer. The GaN-based HFET may also be fabricated without a top barrier layer to obtain an inverted GaN-based HFET.
    Type: Grant
    Filed: July 30, 2001
    Date of Patent: September 23, 2003
    Assignee: The Regents of the University of California
    Inventors: Edward T. Yu, Peter M. Asbeck, Silvanus S. Lau, Xiaozhong Dang
  • Patent number: 6563145
    Abstract: A compound collector double heterojunction bipolar transistor (CCHBT) incorporates a collector comprising two layers: a wide bandgap collector region (e.g., GaAs), and a narrow bandgap collector region (e.g., InGaP). The higher electric field is supported in the wide bandgap region, thereby increasing breakdown voltage and reducing offset voltage. At the same time, the use of wide bandgap material in the depleted portion of the collector, and a higher mobility material toward the end and outside of the depletion region, reduces series resistance as well as knee voltage.
    Type: Grant
    Filed: December 29, 1999
    Date of Patent: May 13, 2003
    Inventors: Charles E. Chang, Richard L. Pierson, Peter J. Zampardi, Peter M. Asbeck
  • Publication number: 20020132435
    Abstract: In one disclosed embodiment, a collector is deposited and a base is grown on the collector, for example, by epitaxially depositing either silicon or silicon-germanium. An emitter is fabricated on the base followed by implant doping an extrinsic base region. For example, the extrinsic base region can be implant doped using boron. The extrinsic base region doping diffuses out during subsequent thermal processing steps in chip fabrication, creating an out diffusion region in the device, which can adversely affect various operating characteristics, such as parasitic capacitance and linearity. The out diffusion is controlled by counter doping the out diffusion region. For example, the counter doped region can be implant doped using arsenic or phosphorous. Also, for example, the counter doped region can be formed using tilt implanting or, alternatively, by implant doping the counter doped region and forming a spacer on the base prior to implanting the extrinsic base region.
    Type: Application
    Filed: March 17, 2001
    Publication date: September 19, 2002
    Applicant: CONEXANT SYSTEMS, INC.
    Inventors: Peter J. Zampardi, Klaus F. Schuegraf, Paul Kempf, Peter M. Asbeck
  • Publication number: 20020079511
    Abstract: An improved HBT of the invention reduces the current blocking effect at the base-collector interface. Nitrogen is incorporated at the base-collector interface in an amount sufficient to reduce the conduction band energy of the collector at the base-collector interface to equal the conduction band energy of the base. In a preferred embodiment, a nitrogen concentration on the order of 2% is used in a thin ˜20nm layer at the base-collector interface. Preferred embodiment HBTs of the invention include both GaAs HBTs and InP transistors in various layer structures, e.g., single and double heterojunction bipolar transistors and blocked hole bipolar transistors.
    Type: Application
    Filed: July 31, 2001
    Publication date: June 27, 2002
    Inventors: Charles W. Tu, Peter M. Asbeck, Kazuhiro Mochizuki, Rebecca Welty
  • Publication number: 20020036287
    Abstract: A GaN-based HFET includes a set of layers all having a common face polarity, i.e., all being either Ga-face or N-face. One of the layers is a thin barrier layer having a first face with a positive charge and a second face with a negative charge thereby causing a potential change to occur between the two faces. The if potential change causes the barrier layer to prevent electron flow from a channel layer into a buffer layer. The GaN-based HFET may also be fabricated without a top barrier layer to obtain an inverted GaN-based HFET.
    Type: Application
    Filed: July 30, 2001
    Publication date: March 28, 2002
    Applicant: The Regents of the University of California
    Inventors: Edward T. Yu, Peter M. Asbeck, Silvanus S. Lau, Xiaozhong Dang
  • Patent number: 5311158
    Abstract: A variety of embodiments of varactor diodes are disclosed ranging from an N.times.N matrix assembly of individually packaged diodes arranged in N rows and columns to a multi-continuous layered varactor. The matrix assembly varactor has N rows of discrete devices electrically coupled in parallel and multiple rows vertically aligned and electrically coupled in series to each other. The overall matrix assembly capacitance equals the individual diode capacitance of such assembly. When used as a tuning component across a tank coil transmission line, the RF voltage across any device in the matrix assembly is equal to the tank voltage divided by N.
    Type: Grant
    Filed: July 9, 1992
    Date of Patent: May 10, 1994
    Assignee: Rockwell International Corporation
    Inventors: Peter M. Asbeck, Richard C. Edwards, Garth D. Hammond, Dale W. Penner
  • Patent number: 5266819
    Abstract: A C-up HBT is made to operate in the microwave/millimeter frequency range by self-aligning the collector uprisers on the base relative to proton damaged emitter regions and the base contacts which minimizes carrier injection into the extrinsic base. The use of about 7-10% indium in the indium gallium arsenide base is sufficient to stop the FREON-12 etch at the base after totally etching through the collector and single self-aligning mask.
    Type: Grant
    Filed: May 13, 1991
    Date of Patent: November 30, 1993
    Assignee: Rockwell International Corporation
    Inventors: Mau Chung F. Chang, Peter M. Asbeck
  • Patent number: 5250826
    Abstract: A III-V compound planar HBT-FET device integrates field effect transistors (FETs) with heterojunction bipolar transistors (HBTs) formed on the same semiconductor substrate. An HBT fabricated on the substrate includes a collector, a base, and an emitter. The HBT emitter comprises a lightly doped layer of a first conductivity type deposited atop a heavily doped base layer of a second conductivity type, a lightly doped emitter cap layer of the first conductivity type deposited atop the emitter layer, and a heavily doped emitter contact layer of the first conductivity type deposited atop the emitter cap layer. A FET, isolated from the HBT by areas of ion implantation, is formed in the layers of material deposited during fabrication of the HBT. The FET has a source and a drain formed in the heavily doped emitter contact layer, a gate recess etched in the emitter contact layer between the source and drain, and a Schottky gate metal contact deposited on the lightly doped emitter cap layer exposed in the gate recess.
    Type: Grant
    Filed: September 23, 1992
    Date of Patent: October 5, 1993
    Assignee: Rockwell International Corporation
    Inventors: Mau-Chung F. Chang, Peter M. Asbeck, Richard L. Pierson, Jr.
  • Patent number: 5185274
    Abstract: Heterojunction bipolar transistor is formed by using a common photoresist mask for self-aligning all critical dimensions including emitter and emitter contact to base contact to proton damaged collector regions beneath base contact and to passivate emitter periphery at same time.
    Type: Grant
    Filed: August 15, 1991
    Date of Patent: February 9, 1993
    Assignee: Rockwell International Corporation
    Inventors: Mau C. F. Chang, Peter M. Asbeck
  • Patent number: 5028549
    Abstract: A method of isolating individual heterojunction bipolar transistors (HBTs) on a wafer increases the current gain which can be obtained when using proton implantation to isolate the transistor. The photoresist pattern which is used to cover the transistor location during isolation implantation is undercut when etching the cap layer. A dielectric is then deposited on the etched surface, including the undercut portion. The photoresist is lifted off and an HBT is fabricated on the wafer in the area which is not covered by the dielectric. The dielectric on the undercut portion confines the emitter current to a region slightly removed from the isolation implant and provides improved current gain.
    Type: Grant
    Filed: April 10, 1989
    Date of Patent: July 2, 1991
    Assignee: Rockwell International
    Inventors: Mau-Chung F. Chang, Peter M. Asbeck
  • Patent number: 4996165
    Abstract: A method for planarizing surfaces in multi-layered semiconductor structures using elevated features in the form of semiconductor materials, such as for forming heterojunctions, or interconnection metal. A process of forming the features includes leaving residual photoresist on the features. After feature formation and definition of transistor or other structure locations, dielectric material is deposited across the structure. Remaining photoresist is subsequently removed along with dielectric deposited thereon leaving dielectric between the features. A layer of polyimide is spun on the structure and into depressions between the dielectric and features. Typically material deposition, etching, dielectric backfilling and spin-coating steps are repeated until a predetermined number of contact or conductivity regions or interconnection metal layers are formed in the desired multi-layered structure.
    Type: Grant
    Filed: April 21, 1989
    Date of Patent: February 26, 1991
    Assignee: Rockwell International Corporation
    Inventors: Mau-Chung F. Chang, Peter M. Asbeck