Abstract: A hardware-facilitated secure software execution environment provides protection of both program instructions and data against unauthorized access and/or execution to maintain confidentiality and integrity of the software or the data during distribution, in external memories, and during execution. The secure computing environment is achieved by using a hardware-based security method and apparatus to provide protection against software privacy and tampering. A Harvard architecture CPU core is instantiated on the same silicon chip along with encryption management unit (EMU) circuitry and secure key management unit (SKU) circuitry. Credential information acquired from one or more sources is combined by the SKU circuitry to generate one or more security keys provided to the EMU for use in decrypting encrypted program instructions and/or data that is obtained from a non-secure, off-chip source such as an external RAM, an information storage device or other network source.

Abstract: A hardware-facilitated secure software execution environment provides protection of both program instructions and data against unauthorized access and/or execution to maintain confidentiality and integrity of the software or the data during distribution, in external memories, and during execution. The secure computing environment is achieved by using a hardware-based security method and apparatus to provide protection against software privacy and tampering. A Harvard architecture CPU core is instantiated on the same silicon chip along with encryption management unit (EMU) circuitry and secure key management unit (SKU) circuitry. Credential information acquired from one or more sources is combined by the SKU circuitry to generate one or more security keys provided to the EMU for use in decrypting encrypted program instructions and/or data that is obtained from a non-secure, off-chip source such as an external RAM, an information storage device or other network source.

Abstract: A data storage system includes memory, a controller, and an Ethernet interface enabling sending and/or receiving Ethernet packets to or from a client system, according to a first protocol. The controller is coupled between the memory and the Ethernet interface and essentially carries out a translation function. Information packets from the client system are translated from a first protocol to a second protocol for use by the memory, and information from the memory is translated from the second protocol to the first protocol for use by the client system as Ethernet packets.

Abstract: The present invention provides a controller system including a common controller, a first interface, a second interface, and an adapter. The first interface is used to receive and to send data according to a first protocol having a format useable by a computer system. The common controller is coupled between the first interface and the second interface to translate between the first protocol and the second protocol, the second protocol is used by a memory coupled to the common controller. The second interface is used to store and to retrieve data from the memory according to the second protocol. The adapter function can be coupled between the memory and the common controller. The memory forms a response to a request by the computer system, with the response including at least one of (A) storing information, (B) retrieving information, and (C) providing status information.

Abstract: A data storage system includes memory, a controller, and an Ethernet interface enabling sending and/or receiving Ethernet packets to or from a client system, according to a first protocol. The controller is coupled between the memory and the Ethernet interface and essentially carries out a translation function. Information packets from the client system are translated from a first protocol to a second protocol for use by the memory, and information from the memory is translated from the second protocol to the first protocol for use by the client system as Ethernet packets.

Abstract: A data hub for facilitating and effecting data transfers between signal processors with high efficiency is disclosed. The data hub receives low priority data transfer instructions from a master CPU and is capable of transferring such low priority data between processors without imposing significant overhead burdens on either the data source or destination. The hub may have the further capability of asynchronously receiving intermediate priority data transfers, storing the received data and transferring it to a destination unit before any further low priority transfers are effected. The hub may have the further capability of asynchronously receiving high priority transfer requests which are effected by the hub before both intermediate and low priority transfers. The hub may be used as a keystone building block for use in linking signal processors.