Patents by Inventor Peter M. Maurer

Peter M. Maurer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method for digital simulation of an electrical circuit
    Patent number: 6131081
    Abstract: A system for digital simulation of an electric circuit is disclosed. The system is event driven, and functions on a gate inversion principle, to stimulate an electric circuit. According to the gate inversion principle, any gates or gate arrangements in the circuit for which the input does not change are not simulated. A machine readable circuit description is generated which includes the gates and the gate arrangements for the circuit. Translation means creates data structures suitable for simulation of the circuit. Simulation means creates a program which schedules the simulation of only those gates or gate arrangements whose outputs change value during the simulation. According to the preferred embodiment, the simulation means uses only inversions of signals from individual gates or gate arrangements to perform the simulation of the circuit. Furthermore, the translation means includes means for removing any NOT gates from the circuit, and means for collapsing all homogeneous connections in the circuit.
    Type: Grant
    Filed: December 16, 1998
    Date of Patent: October 10, 2000
    Assignee: University of South Florida
    Inventor: Peter M. Maurer
  • System and method for digital simulation of an electrical circuit
    Patent number: 5856933
    Abstract: A system for digital simulation of an electric circuit is disclosed. The system is event-driven, and functions on a gate inversion principle, to simulate an electric circuit. According to the gate inversion principle, any gates or gate arrangements in the circuit for which the input does not change are not simulated. A machine readable circuit description is generated which includes the gates and the gate arrangements for the circuit. Translation means creates data structures suitable for simulation of the circuit. Simulation means creates a program which schedules the simulation of only those gates or gate arrangements whose outputs change value during the simulation. According to the preferred embodiment, the simulation means uses only inversions of signals from individual gates or gate arrangements to perform the simulation of the circuit. Furthermore, the translation means includes means for removing any NOT gates from the circuit, and means for collapsing all homogeneous connections in the circuit.
    Type: Grant
    Filed: April 28, 1997
    Date of Patent: January 5, 1999
    Assignee: University of South Florida
    Inventor: Peter M. Maurer