Abstract: A multi-chip module interconnection substrate includes at least two layers of conductive traces separated by an intervening layer of insulating material. The conductive traces include straight segments and diagonal segments. A plurality of conductive vias, each including conductive via wing extensions, allow one to make electrical connections between the various conductive trace layers. The conductive vias are formed such that a narrow, non-conductive, gap exists between the via wing extensions and the conductive traces. The multi-chip module interconnection substrate is then programmed, e.g. in the field, by making electrical connections between the via wing extensions and the conductive traces using e.g. wire bonds or ball bonds formed by conventional wire bonding equipment.

Abstract: An integrated circuit package assembly incorporating an electrostatic discharge (ESD) interposer is disclosed. The assembly includes a semiconductor chip including a plurality of chip input/output terminals. The interposer is formed using a substrate which supports the chip and includes an arrangement having a plurality of integrally formed ESD protection circuits for providing ESD protection to predetermined ones of the chip input/output terminals.

Abstract: A method for fabricating bond pads on a semiconductor device that reduces intermetallic growth between a metallization layer and a bonding layer is discussed. Initially a metallization layer is deposited over a substrate. Following steps include depositing a barrier layer over the metallization layer, masking a portion of the barrier layer, and etching the barrier layer and the metallization layer. Etching of the barrier and masking layers is performed utilizing the barrier layer mask as a mask for both the barrier layer and the metallization layer. Further steps include depositing a non-conductive layer conformally overlying the barrier layer, masking a portion of the non-conductive layer, and etching the non-conductive layer. Etching the non-conductive layer forms an exposed region of the barrier layer. A later step of this method includes forming a bond layer over the exposed region of the barrier layer, with one possible formation method utilizing an electrolysis process.

Abstract: A transfer molded high lead count plastic semiconductor package is described. The packaged IC chip is mounted upon a suitable leadframe and the bonding pads wire bonded to the leadframe fingers. To avoid wire shorting, due to wire sweep during transfer molding, the wires are first coated with an insulative material.

Abstract: A transfer molded high lead count plastic semiconductor package is described. The packaged IC chip is mounted upon a suitable leadframe and the bonding pads wire bonded to the leadframe fingers. To avoid wire shorting, due to wire sweep during transfer molding, the wires are first coated with an insulative material.

Abstract: A mechanical shock and impact resistant ceramic semiconductor package is formed by applying a resilient, non-conductive, non-absorbent, heat-resistant material onto the surfaces of said package. In a dual in-line ceramic package a silicone polymer is discretely applied onto at least one end of the longitudinally opposite end edge surfaces. This renders the package mechanical shock and impact resistant.