Abstract: Embodiments of the disclosure provide integrated circuit (IC) structures with stepped epitaxial regions and methods of forming the same. A method according to the disclosure can include: removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, to expose an underlying sidewall of the semiconductor fin; forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer; removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region; and forming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin.

Abstract: Embodiments of the disclosure provide integrated circuit (IC) structures with stepped epitaxial regions and methods of forming the same. A method according to the disclosure can include: removing a portion of a substrate to form a recess therein, the portion of the substrate being laterally adjacent to a semiconductor fin having a sidewall spacer thereon, to expose an underlying sidewall of the semiconductor fin; forming an epitaxial layer within the recess, such that the epitaxial layer laterally abuts the sidewall of the semiconductor fin below the sidewall spacer; removing a portion of the epitaxial layer to form a stepped epitaxial region adjacent to the semiconductor fin, the stepped epitaxial region including a first region laterally abutting the sidewall of the semiconductor fin, and a second region laterally adjacent to the first region; and forming a gate structure over the stepped epitaxial region and adjacent to the semiconductor fin.

Abstract: A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-.di-elect cons.) dielectric material is used to form an inter-level dielectric (ILD) layer between metallization layers and in which via and trench openings are formed in the low-.di-elect cons. ILD. The dual damascene technique allows for both the via and trench openings to be filled at the same time.

Abstract: A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-.epsilon.) dielectric material is used to form an inter-level dielectric (ILD) layer between metallization layers and in which via and trench openings are formed in the low-.epsilon. ILD. The dual damascene technique allows for both the via and trench openings to be filled at the same time.

Abstract: A light sensing device comprises a photoconductive layer overlaying an array of PN junction diodes integrated within a semiconductor substrate. When a voltage is applied to the device to reverse bias the diodes, the voltage divides across the device in accordance with the capacitance of capacitive elements formed by the photoconductive layer and the junction capacitance of the diodes. When light impinges on the device, charge transfers from the photoconductive layer and accumulates at the underlying junctions at a rate that is directly dependent on the intensity of light incident on the corresponding portion of the photoconductive layer. When a diode reverse breakdown voltage is reached, the corresponding diode conducts. This causes an increase in current through the device, thereby signaling that a desired localized exposure has been attained.

Abstract: A multiple, superposed-channel, solid-state, color image sensor of the "parallel transfer" type includes a plurality of superposed generally "ladder shaped" channels in a semiconductor substrate. One "side rail" of the ladder shape provides the channel structure for a multiple, superposed-channel signal handling device, such as a charge coupled shift register. The "rungs" of the ladder shape provide a plurality of multiple, superposed-channel color image sensing sites, and the other "side rail" of the ladder shape provides a plurality of superposed "anti-bloom" drains, one drain per channel. Electrical contact to a buried channel is provided by a V-groove etching technique. A V-groove extending from the surface of the device into the buried channel provides physical access to the buried channel. A conductor, in ohmic contact with the channel, extends from the bottom of the V-groove to the surface of the device to provide electrical contact with the buried channel.