Patents by Inventor Peter Malcolm Lacey

Peter Malcolm Lacey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240135648
    Abstract: A tessellation method uses tessellation factors defined for each vertex of a patch which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves comparing the vertex tessellation factors to a threshold. If the vertex tessellation factors for either a left vertex or a right vertex, which define an edge of an initial patch, exceed the threshold, the edge is sub-divided by the addition of a new vertex which divides the edge into two parts and two new patches are formed. New vertex tessellation factors are calculated for each vertex in each of the newly formed patches, both of which include the newly added vertex. The method is then repeated for each of the newly formed patches until none of the vertex tessellation factors exceed the threshold.
    Type: Application
    Filed: November 27, 2023
    Publication date: April 25, 2024
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 11928768
    Abstract: A method of controlling the order in which primitives, generated during tessellation, are output by the tessellation unit involves sub-dividing a patch, selecting one of the two sub-patches which are formed by the sub-division and tessellating that sub-patch until no further sub-division is possible before tessellating the other (non-selected) sub-patch. The method is recursively applied at each level of sub-division. Patches are output as primitives at the point in the method where they do not require any further sub-division. The selection of a sub-patch is made based on the values of one or more flags and any suitable tessellation method may be used to determine whether to sub-divide a patch. Methods of controlling the order in which vertices are output by the tessellation unit are also described and these may be used in combination with, or independently of, the method of controlling the primitive order.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: March 12, 2024
    Assignee: Imagination Technologies Limited
    Inventor: Peter Malcolm Lacey
  • Patent number: 11900543
    Abstract: A tessellation method uses both vertex tessellation factors and displacement factors defined for each vertex of a patch, which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves calculating a vertex tessellation factor for each corner vertex in one or more input patches. Tessellation is then performed on the plurality of input patches using the vertex tessellation factors. The tessellation operation involves adding one or more new vertices and calculating a displacement factor for each newly added vertex. A world space parameter for each vertex is subsequently determined by calculating a target world space parameter for each vertex and then modifying the target world space parameter for a vertex using the displacement factor for that vertex.
    Type: Grant
    Filed: October 19, 2022
    Date of Patent: February 13, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 11830143
    Abstract: A tessellation method uses tessellation factors defined for each vertex of a patch which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves comparing the vertex tessellation factors to a threshold. If the vertex tessellation factors for either a left vertex or a right vertex, which define an edge of an initial patch, exceed the threshold, the edge is sub-divided by the addition of a new vertex which divides the edge into two parts and two new patches are formed. New vertex tessellation factors are calculated for each vertex in each of the newly formed patches, both of which include the newly added vertex. The method is then repeated for each of the newly formed patches until none of the vertex tessellation factors exceed the threshold.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: November 28, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Publication number: 20230327682
    Abstract: A method of data compression in which the total size of the compressed data is determined and based on that determination, the bit depth of the input data may be reduced before the data is compressed. The bit depth that is used may be determined by comparing the calculated total size to one or more pre-defined threshold values to generate a mapping parameter. The mapping parameter is then input to a remapping element that is arranged to perform the conversion of the input data and then output the converted data to a data compression element. The value of the mapping parameter may be encoded into the compressed data so that it can be extracted and used when subsequently decompressing the data.
    Type: Application
    Filed: June 12, 2023
    Publication date: October 12, 2023
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Publication number: 20230274503
    Abstract: Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.
    Type: Application
    Filed: May 1, 2023
    Publication date: August 31, 2023
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Publication number: 20230232009
    Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 7-bits or 8-bits and generating error values for each of the converted values. Two of the 8-bit output channels comprise a combination of a converted 7-bit value and one of the bits from the fourth input channel. A third 8-bit output channel comprises the converted 8-bit value and the fourth 8-bit output channel comprises the error values. In various examples, the bits of the error values may be interleaved when they are packed into the fourth output channel.
    Type: Application
    Filed: March 17, 2023
    Publication date: July 20, 2023
    Inventors: Ilaria Martinelli, Jeff Bond, Simon Fenney, Peter Malcolm Lacey, Gregory Clark
  • Patent number: 11676337
    Abstract: Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: June 13, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 11676336
    Abstract: A method of generating identifiers (IDs) for primitives and optionally vertices during tessellation. The IDs include a binary sequence of bits that represents the sub-division steps taken during the tessellation process and so encodes the way in which tessellation has been performed. Such an ID may subsequently be used to generate a random primitive or vertex and hence recalculate vertex data for that primitive or vertex.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: June 13, 2023
    Assignee: Imagination Technologies Limited
    Inventor: Peter Malcolm Lacey
  • Patent number: 11677415
    Abstract: A method of data compression in which the total size of the compressed data is determined and based on that determination, the bit depth of the input data may be reduced before the data is compressed. The bit depth that is used may be determined by comparing the calculated total size to one or more pre-defined threshold values to generate a mapping parameter. The mapping parameter is then input to a remapping element that is arranged to perform the conversion of the input data and then output the converted data to a data compression element. The value of the mapping parameter may be encoded into the compressed data so that it can be extracted and used when subsequently decompressing the data.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: June 13, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 11611754
    Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 7-bits or 8-bits and generating error values for each of the converted values. Two of the 8-bit output channels comprise a combination of a converted 7-bit value and one of the bits from the fourth input channel. A third 8-bit output channel comprises the converted 8-bit value and the fourth 8-bit output channel comprises the error values. In various examples, the bits of the error values may be interleaved when they are packed into the fourth output channel.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: March 21, 2023
    Assignee: Imagination Technologies Limited
    Inventors: Ilaria Martinelli, Jeff Bond, Simon Fenney, Peter Malcolm Lacey, Gregory Clark
  • Publication number: 20230066361
    Abstract: A tessellation method uses both vertex tessellation factors and displacement factors defined for each vertex of a patch, which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves calculating a vertex tessellation factor for each corner vertex in one or more input patches. Tessellation is then performed on the plurality of input patches using the vertex tessellation factors. The tessellation operation involves adding one or more new vertices and calculating a displacement factor for each newly added vertex. A world space parameter for each vertex is subsequently determined by calculating a target world space parameter for each vertex and then modifying the target world space parameter for a vertex using the displacement factor for that vertex.
    Type: Application
    Filed: October 19, 2022
    Publication date: March 2, 2023
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Publication number: 20220392139
    Abstract: A method of controlling the order in which primitives, generated during tessellation, are output by the tessellation unit involves sub-dividing a patch, selecting one of the two sub-patches which are formed by the sub-division and tessellating that sub-patch until no further sub-division is possible before tessellating the other (non-selected) sub-patch. The method is recursively applied at each level of sub-division. Patches are output as primitives at the point in the method where they do not require any further sub-division. The selection of a sub-patch is made based on the values of one or more flags and any suitable tessellation method may be used to determine whether to sub-divide a patch. Methods of controlling the order in which vertices are output by the tessellation unit are also described and these may be used in combination with, or independently of, the method of controlling the primitive order.
    Type: Application
    Filed: August 5, 2022
    Publication date: December 8, 2022
    Inventor: Peter Malcolm Lacey
  • Patent number: 11501494
    Abstract: A tessellation method uses both vertex tessellation factors and displacement factors defined for each vertex of a patch, which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves calculating a vertex tessellation factor for each corner vertex in one or more input patches. Tessellation is then performed on the plurality of input patches using the vertex tessellation factors. The tessellation operation involves adding one or more new vertices and calculating a displacement factor for each newly added vertex. A world space parameter for each vertex is subsequently determined by calculating a target world space parameter for each vertex and then modifying the target world space parameter for a vertex using the displacement factor for that vertex.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: November 15, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Publication number: 20220327780
    Abstract: A tessellation method uses tessellation factors defined for each vertex of a patch which may be a quad, a triangle or an isoline. The method is implemented in a computer graphics system and involves comparing the vertex tessellation factors to a threshold. If the vertex tessellation factors for either a left vertex or a right vertex, which define an edge of an initial patch, exceed the threshold, the edge is sub-divided by the addition of a new vertex which divides the edge into two parts and two new patches are formed. New vertex tessellation factors are calculated for each vertex in each of the newly formed patches, both of which include the newly added vertex. The method is then repeated for each of the newly formed patches until none of the vertex tessellation factors exceed the threshold.
    Type: Application
    Filed: June 20, 2022
    Publication date: October 13, 2022
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Patent number: 11468622
    Abstract: A method of controlling the order in which primitives generated during tessellation are output by the tessellation unit involves sub-dividing a patch, selecting one of the two sub-patches which are formed by the sub-division and tessellating that sub-patch until no further sub-division is possible before tessellating the other (non-selected) sub-patch. The method is recursively applied at each level of sub-division. Patches are output as primitives at the point in the method where they do not require any further sub-division. The selection of a sub-patch is made based on the values of one or more flags and any suitable tessellation method may be used to determine whether to sub-divide a patch. Methods of controlling the order in which vertices are output by the tessellation unit are also described and these may be used in combination with, or independently of, the method of controlling the primitive order.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: October 11, 2022
    Assignee: Imagination Technologies Limited
    Inventor: Peter Malcolm Lacey
  • Publication number: 20220270320
    Abstract: Implementations of blender hardware perform both domain shading and blending and whilst some vertices may not require blending, all vertices require domain shading. The blender hardware includes a cache and/or a content addressable memory and these data structures are used to reduce duplicate domain shading operations.
    Type: Application
    Filed: May 13, 2022
    Publication date: August 25, 2022
    Inventors: Peter Malcolm Lacey, Simon Fenney, Tobias Hector, Ian King
  • Publication number: 20220270325
    Abstract: Hardware tessellation units include a sub-division logic block that comprises hardware logic arranged to perform a sub-division of a patch into two (or more) sub-patches. The hardware tessellation units also include a decision logic block that is configured to determine whether a patch is to be sub-divided or not and one or more hardware elements that control the order in which tessellation occurs. In various examples, this hardware element is a patch stack that operates a first-in-last-out scheme and in other examples, there are one or more selection logic blocks that are configured to receive patch data for more than one patch or sub-patch and output the patch data for a selected one of the received patches or sub-patches.
    Type: Application
    Filed: April 29, 2022
    Publication date: August 25, 2022
    Inventors: Peter Malcolm Lacey, Simon Fenney
  • Publication number: 20220232217
    Abstract: A method of converting 10-bit pixel data (e.g. 10:10:10:2 data) into 8-bit pixel data involves converting the 10-bit values to 7-bits or 8-bits and generating error values for each of the converted values. Two of the 8-bit output channels comprise a combination of a converted 7-bit value and one of the bits from the fourth input channel. A third 8-bit output channel comprises the converted 8-bit value and the fourth 8-bit output channel comprises the error values. In various examples, the bits of the error values may be interleaved when they are packed into the fourth output channel.
    Type: Application
    Filed: April 5, 2022
    Publication date: July 21, 2022
    Inventors: Ilaria Martinelli, Jeff Bond, Simon Fenney, Peter Malcolm Lacey, Gregory Clark
  • Publication number: 20220222894
    Abstract: A method of generating identifiers (IDs) for primitives and optionally vertices during tessellation. The IDs include a binary sequence of bits that represents the sub-division steps taken during the tessellation process and so encodes the way in which tessellation has been performed. Such an ID may subsequently be used to generate a random primitive or vertex and hence recalculate vertex data for that primitive or vertex.
    Type: Application
    Filed: March 29, 2022
    Publication date: July 14, 2022
    Inventor: Peter Malcolm Lacey