Abstract: Different processor architectures are described to evaluate and track dependencies required by instructions. The processors may hold or queue instructions that require output of other instructions until required data and resources are available which may remove the requirement of NOPs in the instruction memory to resolve dependencies and pipeline hazards. The processor may divide instruction data into bundles for parallel execution and provide speculative execution. The processor may include various components to implement an evaluation unit, execution unit and termination unit.

Abstract: The processor chip can have a pre-execution pipeline sharing a plurality of resources including at least one resource of interest, a resource tracker having more than one credit unit associated with each one of said at least one resource of interest. The method can include: decoding the instruction data to determine a resource requirement including a quantity of virtual credits required from the credit units for the at least one resource of interest, checking the resource tracker for an availability of said quantity of virtual credits and, if the availability of the amount of said virtual credits is established, i) dispatching the instruction data, and ii) subtracting the quantity of said credits from the resource tracker.

Abstract: The method can be performed in a processor integrated circuit having an instruction decoder and a plurality of shared resources, a resource tracker circuit having a plurality of credit units associated with corresponding ones of the shared resources in a manner to be updatable based on availability of the shared resources, and a resource matcher connected to receive a resource requirement signal from the decoder and connected to receive a resource availability signal from the resource tracker. The method can include performing a determination of whether or not the resource requirement signal matches the resource availability signal, and, upon a positive determination, dispatching corresponding instruction data, updating the status of a corresponding one or more of the credit units, and preventing the resource matcher from performing a subsequent determination for a given period of time after the positive determination.

Abstract: The method can be performed in a processor integrated circuit having an instruction decoder and a plurality of shared resources, a resource tracker having a plurality of credit units associated to corresponding ones of the shared resources in a manner to be updatable based on availability of the shared resources, a resource matcher connected to receive a resource requirement signal from the decoder and connected to receive a resource availability signal from the resource tracker. The method can include: performing a determination of whether or not the resource requirement signal matches the resource availability signal, and, upon a positive determination, dispatching a corresponding instruction data, updating the status of a corresponding one or more of the credit units, and preventing the resource matcher from performing a subsequent determination for given period of time after the positive determination.

Abstract: The processor chip can have a pre-execution pipeline sharing a plurality of resources including at least one resource of interest, a resource tracker having more than one credit unit associated to each one of said at least one resource of interest. The method can include: decoding the instruction data to determine a resource requirement including a quantity of virtual credits required from the credit units for the at least one resource of interest, checking the resource tracker for an availability of said quantity of virtual credits and, if the availability of the amount of said virtual credits is established, i) dispatching the instruction data, and ii) subtracting the quantity of said credits from the resource tracker.

Abstract: Different processor architectures are described to evaluate and track dependencies required by instructions. The processors may hold or queue instructions that require output of other instructions until required data and resources are available which may remove the requirement of NOPs in the instruction memory to resolve dependencies and pipeline hazards. The processor may divide instruction data into bundles for parallel execution and provide speculative execution. The processor may include various components to implement an evaluation unit, execution unit and termination unit.

Abstract: A system and method for multi-branch switching are provided. A memory has stored therein a program comprising at least one sequence of instructions, the at least one sequence of instructions comprising a plurality of branch instructions, at least one branch of the program reached upon execution of each one of the plurality of branch instructions. The processor is configured for fetching the plurality of branch instructions from the memory, separately buffering each branch of the program associated with each one of the fetched branch instructions, evaluating the fetched branch instructions in parallel, and executing the evaluated branch instructions in parallel.

Abstract: A method and a system is provided for Coordinate Rotation Digital Computer (CORDIC) based matrix inversion of input digital signal streams from multiple antennas using an bi-directional ring-bus architecture. The bi-directional ring bus includes a first ring bus having signals flow in a clockwise direction, and a second ring bus having signals flow in a counter-clockwise direction. An I/O controller is coupled to the first and the second ring bus, respectively. A plurality of processing elements (PEs), where each of the plurality of PEs is coupled to the first and the second ring bus, respectively, wherein each of the plurality of PEs includes at least one CORDIC core for performing CORDIC iterations on the plurality of input digital stream signals to produce inversed matrix signals.

Abstract: A method and a system is provided for Coordinate Rotation Digital Computer (CORDIC) based matrix inversion of input digital signal streams from multiple antennas using an bi-directional ring-bus architecture. The bi-directional ring bus includes a first ring bus having signals flow in a clockwise direction, and a second ring bus having signals flow in a counter-clockwise direction. An I/O controller is coupled to the first and the second ring bus, respectively. A plurality of processing elements (PEs), where each of the plurality of PEs is coupled to the first and the second ring bus, respectively, wherein each of the plurality of PEs includes at least one CORDIC core for performing CORDIC iterations on the plurality of input digital stream signals to produce inversed matrix signals.