Abstract: A method of and operating architectural enhancement for combining photonic and data packet-based networks to be unified or integrated as a single device and with a common software control plane, enabling increased utilization of such combined networks and in particular of optical path data flow capacity.

Abstract: A method of and operating architectural enhancement for combining photonic and data packet-based networks to be unified or integrated as a single device and with a common software control plane, enabling increased utilization of such combined networks and in particular of optical path data flow capacity.

Abstract: Apparatus for and method of enhancing the performance of multi-port internal cached DRAMs and the like by providing for communicating to system I/O resources messages sent by other such resources and the message location within the DRAM array, and further providing for efficient internal data bus usage in accommodating for both small and large units of data transfer.

Abstract: An electronic circuit board assembly and method that enable close stacking and cooling of closely positioned pluralities of similar electronic I/O or memory boards and requiring high speed communication between the boards, such as high speed switching amongst the I/O terminals of the boards or CPU processing, and having an upper and a lower set of similar spaced groups of closely spaced vertical boards; powering terminals aligned along the upper edges of the upper set of boards, and along the lower edges of the lower set of boards, and terminals for connection with a switching fabric disposed along the lower edges of the upper set of boards and the upper edges of the lower set of boards; power backing planes mounted to power and support the lateral edges of the respective sets of groups of boards and extending across the upper and lower sections of the frame; and a plurality of parallel closely spaced vertical switching fabric boards comprising switching fabric (or CPU processing boards) and centrally mounted

Abstract: A novel networking architecture and technique for reducing system latency caused, at least in part, by access contention for usage of common bus and memory facilities, wherein a separate data processing and queue management forwarding engine and queue manager are provided for each I/O module to process packet/cell control information and delivers queuing along a separate path that eliminates contention with other resources and is separate from the transfer of packet/cell data into and from the memory.