Abstract: A method and system is used to determine the correct rounding of a floating point function. The method involves performing the floating point function to a higher precision than required and examining the portion of extra precision in the result known as the discriminant. If a critical pattern is found in the discriminant, this indicates that standard rounding may give an incorrect result and further calculation is needed. The method can work for various rounding modes and types of floating point representations. The method can be implemented in a system as part of a processor instruction set or any combination of hardware, microcode, and software.

Abstract: A system to optimize code for a family of related functions. The system recognizes a function call as being a member of a family of related functions. For the member function, the system replaces the member call with corresponding family-start and member-finish function calls.

Abstract: Consider a set of functions, each of whose calculations are almost identical. A common example is the set of trigonometric functions sine, cosine, and tangent. Each of these functions is computed by first performing argument reduction and some preliminary calculations, which are identical for all members of the set. A few unique instructions are performed at the end for each of the functions in the set. Normally, when such functions are encountered, a separate sequence of instructions is called for each function even if the functions appear in close proximity. This results in duplicate instructions being performed which increases execution time and length of compiled program. Specialized functions exists to minimize execution, but programs with such specialized function calls suffer from non-portability. The present invention includes a method and a system to optimize function calls for faster execution while maintaining portability.

Abstract: A method and system is used to determine the correct rounding of a floating point function. The method involves performing the floating point function to a higher precision than required and examining the portion of extra precision in the result known as the discriminant. If a critical pattern is found in the discriminant, this indicates that standard rounding may give an incorrect result and further calculation is needed. The method can work for various rounding modes and types of floating point representations. The method can be implemented in a system as part of a processor instruction set or any combination of hardware, microcode, and software.

Abstract: A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

Abstract: Consider a set of functions, each of whose calculations are almost identical. A common example is the set of trigonometric functions sine, cosine, and tangent. Each of these functions is computed by first performing argument reduction and some preliminary calculations, which are identical for all members of the set. A few unique instructions are performed at the end for each of the functions in the set. Normally, when such functions are encountered, a separate sequence of instructions is called for each function even if the functions appear in close proximity. This results in duplicate instructions being performed which increases execution time and length of compiled program. Specialized functions exists to minimize execution, but programs with such specialized function calls suffer from non-portability. The present invention includes a method and a system to optimize function calls for faster execution while maintaining portability.

Abstract: A system to optimize code for a family of related functions. The system recognizes a function call as being a member of a family of related functions. For the member function, the system replaces the member call with corresponding family-start and member-finish function calls.

Abstract: A compiler includes a real register allocation stage, an optimization stage and a final code stage. The real register allocation stage is configured to generate intermediate code from a basic block of source code. Physical registers, instead of virtual registers, are allocated to operands from the generated intermediate code, and the operands are stored in the physical registers. Then, the intermediate code is optimized, and machine readable code is generated from the intermediated code using the optimized registers in the final code stage. By allocating physical registers in the front-end of the compiler, instead of just prior to generating the machine-readable code, compiling time and memory needed for compiling source code is reduced.

Abstract: A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

Abstract: The present invention is generally directed to a system and method for supporting speculative execution of an instruction set for a central processing unit (CPU) including non-speculative and speculative instructions. In accordance with one aspect of the invention a method includes the steps of evaluating the instructions of the program to determine whether the individual instructions are speculative or non-speculative, and assessing each of the speculative instructions to determine whether it generates an exception. For each of the speculative instructions that generates an exception, the method then encode a deferred exception token (DET) into an unused register value of a register of the CPU. In accordance with another aspect of the invention, a system is provided, which system includes circuitry configured to evaluate the instructions of the instruction set to determine whether the individual instructions are speculative or non-speculative.

Abstract: A floating-point unit of a computer includes a floating-point computation unit, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

Abstract: A floating-point unit of a computer includes a floating-point computation it, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control information. Different floating-point operations may be associated with different status fields. Subfields of the floating-point status register may be updated dynamically during operation. The control bits of the alternate status fields may include a trap disable bit for deferring interruptions during speculative execution. A widest range exponent control bit in the status fields may be used to prevent interruptions when the exponent of an intermediate result is within the range of the register format but exceeds the range of the memory format. The floating-point data may be stored in big endian or little endian format.

Abstract: A floating point arithmetic unit for correctly rounding a quotient or a square root of high precision numbers to the floating point number closest to the exact result is disclosed. The invention is generally applicable to round results to a precision greater than that provided by the floating point hardware. Prior to rounding, the hardware within the floating point unit produces a high precision mantissa with all but the last few digits correct. The rounding technique according to the invention is then used to produce a correctly rounded result using an enhanced Tuckerman test. Unlike a conventional Tuckerman test, the enhanced Tuckerman test determines the last few ULPs for both square root and division while checking for early termination. The advantage of checking for early termination is that the computation time needed to make the rounding decision can be significantly reduced.

Abstract: A floating point processing system which uses a multiplier unit and an adder unit to perform properly rounded quad precision floating point arithmetic operations using double-extended hardware. The floating point processing system includes quad data muxes for converting a quantity between a quad precision representation and a two double-extended precision quantities and vice versa, wherein the sum, if added at infinite precision, of the two double-extended precision quantities is equal to the quad precision quantity. The floating point processing system further include hardware for performing arithmetic operations on double-extended precision quantities.

Abstract: A floating point processing system which uses a multiplier unit and an adder unit to perform floating point division and square root operations using both a conventional and a modified form of the Newton-Raphson method. The modified form of the Newton-Raphson method is used in place of the final iteration of the conventional Newton-Raphson so as to compute high precision approximated results with a substantial improvement in speed. The invention computes approximated results faster and simplifies hardware requirements because no multiplications of numbers of the precision of the result are required.

Abstract: A floating point processing system which uses a multiplier unit and an adder unit to perform floating point division and square root operations using both a conventional and a modified form of the Newton-Raphson method. The modified form of the Newton-Raphson method is used in place of the final iteration of the conventional Newton-Raphson so as to compute high precision approximated results with a substantial improvement in speed. The invention computes approximated results faster and simplifies hardware requirements because no multiplications of numbers of the precision of the result are required.