Patents by Inventor Peter McColgan
Peter McColgan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088900Abstract: An apparatus includes a data processing array having a plurality of array tiles. The plurality of array tiles include a plurality of compute tiles. The compute tiles include a core coupled to a random-access memory (RAM) in a same compute tile and to a RAM of at least one other compute tile. The data processing array is subdivided into a plurality of partitions. Each partition includes a plurality of array tiles including at least one of the plurality of compute tiles. The apparatus includes a plurality of clock gate circuits being programmable to selectively gate a clock signal provided to a respective one of the plurality of partitions.Type: ApplicationFiled: November 14, 2023Publication date: March 14, 2024Applicant: Xilinx, Inc.Inventors: Juan J. Noguera Serra, Tim Tuan, Javier Cabezas Rodriguez, David Clarke, Peter McColgan, Zachary Blaise Dickman, Saurabh Mathur, Amarnath Kasibhatla, Francisco Barat Quesada
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Patent number: 11848670Abstract: An apparatus includes a data processing array having a plurality of array tiles. Each array tile can include a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile. Each adjacent memory interface of each array tile can include isolation logic that is programmable to allow the circuitry disposed within the adjacent array tile to access the RAM or prevent the circuitry disposed within the adjacent array tile from accessing the RAM. The data processing array can be subdivided into a plurality of partitions wherein the isolation logic of the adjacent memory interfaces is programmed to prevent array tiles from accessing RAMs across a boundary between the plurality of partitions.Type: GrantFiled: April 15, 2022Date of Patent: December 19, 2023Assignee: Xilinx, Inc.Inventors: Juan J. Noguera Serra, Tim Tuan, Javier Cabezas Rodriguez, David Clarke, Peter McColgan, Zachary Blaise Dickman, Saurabh Mathur, Amarnath Kasibhatla, Francisco Barat Quesada
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Publication number: 20230376437Abstract: An integrated circuit (IC) can include a data processing array including a plurality of compute tiles arranged in a grid. The IC can include an array interface coupled to the data processing array. The array interface includes a plurality of interface tiles. Each interface tile includes a plurality of direct memory access circuits. The IC can include a network-on-chip (NoC) coupled to the array interface. Each direct memory access circuit is communicatively linked to the NoC via an independent communication channel.Type: ApplicationFiled: May 17, 2022Publication date: November 23, 2023Applicant: Xilinx, Inc.Inventors: David Patrick Clarke, Peter McColgan, Juan J. Noguera Serra, Tim Tuan, Saurabh Mathur, Amarnath Kasibhatla, Javier Cabezas Rodriguez, Pedro Miguel Parola Duarte, Zachary Blaise Dickman
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Publication number: 20230336179Abstract: An apparatus includes a data processing array having a plurality of array tiles. Each array tile can include a random-access memory (RAM) having a local memory interface accessible by circuitry within the array tile and an adjacent memory interface accessible by circuitry disposed within an adjacent array tile. Each adjacent memory interface of each array tile can include isolation logic that is programmable to allow the circuitry disposed within the adjacent array tile to access the RAM or prevent the circuitry disposed within the adjacent array tile from accessing the RAM. The data processing array can be subdivided into a plurality of partitions wherein the isolation logic of the adjacent memory interfaces is programmed to prevent array tiles from accessing RAMs across a boundary between the plurality of partitions.Type: ApplicationFiled: April 15, 2022Publication date: October 19, 2023Applicant: Xilinx, Inc.Inventors: Juan J. Noguera Serra, Tim Tuan, Javier Cabezas Rodriguez, David Clarke, Peter McColgan, Zachary Blaise Dickman, Saurabh Mathur, Amarnath Kasibhatla, Francisco Barat Quesada
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Patent number: 11730325Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.Type: GrantFiled: September 7, 2021Date of Patent: August 22, 2023Assignee: XILINX, INC.Inventors: Peter McColgan, Goran Hk Bilski, Juan J. Noguera Serra, Jan Langer, Baris Ozgul, David Clarke
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Publication number: 20230079307Abstract: This application generally relates to defining, displaying and interacting with tags in a 3D model. In an embodiment, a method includes generating, by a system including a processor, a three-dimensional model of an environment based on sets of aligned three-dimensional data captured from the environment, and associating tags with defined locations of the three-dimensional model, wherein the tags are respectively represented by tag icons that are spatially aligned with the defined locations of the three-dimensional model as included in different representations of the three-dimensional model rendered via an interface of a device, wherein the different representations correspond to different perspectives of the three-dimensional model, and wherein selection of the tag icons causes the tags respectively associated therewith to be rendered at the device.Type: ApplicationFiled: August 16, 2022Publication date: March 16, 2023Applicant: Matterport, Inc.Inventors: James Mildrew, Matthew Tschudy Bell, Dustin Michael Cook, Preston Cowley, Lester Lee, Peter McColgan, Daniel Prochazka, Brian Schulman, James Sundra, Alan Tan
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Publication number: 20230053537Abstract: Using multiple overlays with a data processing array includes loading an application in a data processing array. The data processing array includes a plurality of compute tiles each having a processor. The application specifies kernels executable by the processors and implements stream channels that convey data to the plurality of compute tiles. During runtime of the application, a plurality of overlays are sequentially implemented in the data processing array. Each overlay implements a different mode of data movement in the data processing array via the stream channels. For each overlay implemented, a workload is performed by moving data to the plurality of compute tiles based on the respective mode of data movement.Type: ApplicationFiled: August 15, 2022Publication date: February 23, 2023Applicant: Xilinx, Inc.Inventors: Baris Ozgul, David Clarke, Peter McColgan, Stephan Munz, Dylan Stuart, Pedro Miguel Parola Duarte, Juan J. Noguera Serra
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Publication number: 20230059970Abstract: Examples herein describe techniques for reducing the amount of memory used during weight sparsity. When decompressing the weights, the uncompressed weight data typically has many zero values. By knowing the location of these zero values (e.g., their indices in a weight matrix), the processor core can prune some of the activations (e.g., logically reduce the size of the activation matrix) which improves the efficiency of the processor core. In embodiments herein, the processor core includes logic for identifying the indices of the non-zero value after decompressing the compressed weights. These indices can then be used to prune the activations to improve the efficiency of the processor core.Type: ApplicationFiled: July 18, 2022Publication date: February 23, 2023Inventors: Francisco Barat QUESADA, Baris OZGUL, Dylan STUART, Stephan MUNZ, Zachary DICKMAN, Javier CABEZAS RODRIGUEZ, David Patrick CLARKE, Pedro Miguel Parola DUARTE, Peter MCCOLGAN, Juan J. NOGUERA SERRA
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Patent number: 11520717Abstract: An integrated circuit having a data processing engine (DPE) array can include a plurality of memory tiles. A first memory tile can include a first direct memory access (DMA) engine, a first random-access memory (RAM) connected to the first DMA engine, and a first stream switch coupled to the first DMA engine. The first DMA engine may be coupled to a second RAM disposed in a second memory tile. The first stream switch may be coupled to a second stream switch disposed in the second memory tile.Type: GrantFiled: March 9, 2021Date of Patent: December 6, 2022Assignee: Xilinx, Inc.Inventors: David Clarke, Peter McColgan, Zachary Dickman, Jose Marques, Juan J. Noguera Serra, Tim Tuan, Baris Ozgul, Jan Langer
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Patent number: 11443091Abstract: An integrated circuit includes a plurality of data processing engines (DPEs) DPEs. Each DPE may include a core configured to perform computations. A first DPE of the plurality of DPEs includes a first core coupled to an input cascade connection of the first core. The input cascade connection is directly coupled to a plurality of source cores of the plurality of DPEs. The input cascade connection includes a plurality of inputs, wherein each of the plurality of inputs is connected to a cascade output of a different one of the plurality of source cores. The input cascade connection is programmable to enable a selected one of the plurality of inputs.Type: GrantFiled: July 31, 2020Date of Patent: September 13, 2022Assignee: Xilinx, Inc.Inventors: Peter McColgan, Baris Ozgul, David Clarke, Tim Tuan, Juan J. Noguera Serra, Goran H. K. Bilski, Jan Langer, Sneha Bhalchandra Date, Stephan Munz, Jose Marques
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Patent number: 11422671Abstract: This application generally relates to defining, displaying and interacting with tags in a 3D model. In an embodiment, a method includes generating, by a system including a processor, a three-dimensional model of an environment based on sets of aligned three-dimensional data captured from the environment, and associating tags with defined locations of the three-dimensional model, wherein the tags are respectively represented by tag icons that are spatially aligned with the defined locations of the three-dimensional model as included in different representations of the three-dimensional model rendered via an interface of a device, wherein the different representations correspond to different perspectives of the three-dimensional model, and wherein selection of the tag icons causes the tags respectively associated therewith to be rendered at the device.Type: GrantFiled: September 15, 2020Date of Patent: August 23, 2022Assignee: Matterport, Inc.Inventors: James Mildrew, Matthew Tschudy Bell, Dustin Michael Cook, Preston Cowley, Lester Lee, Peter McColgan, Daniel Prochazka, Brian Schulman, James Sundra, Alan Tan
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Patent number: 11336287Abstract: An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.Type: GrantFiled: March 9, 2021Date of Patent: May 17, 2022Assignee: Xilinx, Inc.Inventors: Javier Cabezas Rodriguez, Juan J. Noguera Serra, David Clarke, Sneha Bhalchandra Date, Tim Tuan, Peter McColgan, Jan Langer, Baris Ozgul
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Patent number: 11323391Abstract: Some examples described herein relate to multi-port stream switches of data processing engines (DPEs) of an electronic device, such as a programmable device. In an example, a programmable device includes a plurality of DPEs. Each DPE of the DPEs includes a hardened processor core and a stream switch. The stream switch is connected to respective stream switches of ones of the DPEs that neighbor the respective DPE in respective ones of directions. The stream switch has input ports associated with each direction of the directions and has output ports associated with each direction of the directions. For each direction of the directions, each input port of the input ports associated with the respective direction is selectively connectable to one of the output ports associated with the respective direction.Type: GrantFiled: March 27, 2020Date of Patent: May 3, 2022Assignee: XILINX, INC.Inventors: Peter McColgan, David Clarke, Goran Hk Bilski, Juan J. Noguera Serra, Baris Ozgul, Jan Langer, Tim Tuan
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Patent number: 11296707Abstract: An integrated circuit can include a data processing engine (DPE) array having a plurality of tiles. The plurality of tiles can include a plurality of DPE tiles, wherein each DPE tile includes a stream switch, a core configured to perform operations, and a memory module. The plurality of tiles can include a plurality of memory tiles, wherein each memory tile includes a stream switch, a direct memory access (DMA) engine, and a random-access memory. The DMA engine of each memory tile may be configured to access the random-access memory within the same memory tile and the random-access memory of at least one other memory tile. Selected ones of the plurality of DPE tiles may be configured to access selected ones of the plurality of memory tiles via the stream switches.Type: GrantFiled: March 9, 2021Date of Patent: April 5, 2022Assignee: Xilinx, Inc.Inventors: Javier Cabezas Rodriguez, Juan J. Noguera Serra, David Clarke, Sneha Bhalchandra Date, Tim Tuan, Peter McColgan, Jan Langer, Baris Ozgul
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Publication number: 20220015588Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.Type: ApplicationFiled: September 7, 2021Publication date: January 20, 2022Inventors: Peter MCCOLGAN, Goran Hk BILSKI, Juan J. NOGUERA SERRA, Jan LANGER, Baris OZGUL, David CLARKE
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Patent number: 11113223Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.Type: GrantFiled: April 3, 2018Date of Patent: September 7, 2021Assignee: XILINX, INC.Inventors: Peter McColgan, Goran H K Bilski, Juan J. Noguera Serra, Jan Langer, Baris Ozgul, David Clarke
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Patent number: 10990552Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the engines. To transmit processed data, a data processing engine identifies a destination processing engine in the array. Once identified, the data processing engine can transmit the processed data using a reserved point-to-point communication path in the interconnect that couples the source and destination data processing engines.Type: GrantFiled: April 3, 2018Date of Patent: April 27, 2021Assignee: XILINX, INC.Inventors: Goran Hk Bilski, Peter McColgan, Juan J. Noguera Serra, Baris Ozgul, Jan Langer, Richard L. Walke, Ralph D. Wittig, Kornelis A. Vissers, Philip B. James-Roxby, Christopher H. Dick
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Publication number: 20210064217Abstract: This application generally relates to defining, displaying and interacting with tags in a 3D model. In an embodiment, a method includes generating, by a system including a processor, a three-dimensional model of an environment based on sets of aligned three-dimensional data captured from the environment, and associating tags with defined locations of the three-dimensional model, wherein the tags are respectively represented by tag icons that are spatially aligned with the defined locations of the three-dimensional model as included in different representations of the three-dimensional model rendered via an interface of a device, wherein the different representations correspond to different perspectives of the three-dimensional model, and wherein selection of the tag icons causes the tags respectively associated therewith to be rendered at the device.Type: ApplicationFiled: September 15, 2020Publication date: March 4, 2021Inventors: James Mildrew, Matthew Tschudy Bell, Dustin Michael Cook, Preston Cowley, Lester Lee, Peter McColgan, Daniel Prochazka, Brian Schulman, James Sundra, Alan Tan
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Patent number: 10775959Abstract: This application generally relates to defining, displaying and interacting with tags in a 3D model. In an embodiment, a method includes generating, by a system including a processor, a three-dimensional model of an environment based on sets of aligned three-dimensional data captured from the environment, and associating tags with defined locations of the three-dimensional model, wherein the tags are respectively represented by tag icons that are spatially aligned with the defined locations of the three-dimensional model as included in different representations of the three-dimensional model rendered via an interface of a device, wherein the different representations correspond to different perspectives of the three-dimensional model, and wherein selection of the tag icons causes the tags respectively associated therewith to be rendered at the device.Type: GrantFiled: October 17, 2018Date of Patent: September 15, 2020Assignee: Matterport, Inc.Inventors: James Mildrew, Matthew Tschudy Bell, Dustin Michael Cook, Preston Cowley, Lester Lee, Peter McColgan, Daniel Prochazka, Brian Schulman, James Sundra, Alan Tan
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Patent number: 10635622Abstract: A device may include a plurality of data processing engines, a subsystem, and an SoC interface block coupled to the plurality of data processing engines and the subsystem. The SoC interface block may be configured to exchange data between the subsystem and the plurality of data processing engines.Type: GrantFiled: April 3, 2018Date of Patent: April 28, 2020Assignee: XILINX, INC.Inventors: Goran H. K. Bilski, Juan J. Noguera Serra, David Clarke, Tim Tuan, Peter McColgan, Zachary Dickman, Baris Ozgul, Jan Langer