Abstract: A method and apparatus of managing a memory (2) having a number of pages (5) involves mapping the physical pages (5) to corresponding pages (4) in a logical address space (1) using a map table (3). When the number of pages utilised by an application increases or decreases, or if an application is deleted or a new application is loaded, the physical pages used by the remaining applications are unchanged, but the logical pages are moved so that the logical pages used by a single application are contiguous and so that the unused pages are contiguous. Thus, after moving the logical pages, the mapping of the logical pages to the physical pages is updated and a free page pointer (6) indicates the next available free logical page.

Abstract: A microcontroller (100) has a CPU (102) and memory (104). Memory (104) contains a memory array (200). A large portion of the array (200) is used to contain functional data for the CPU (102), but the array (200) also contains one or a few rows of memory content parity information. Once the array (200) is written with lasting data and/or software, a parity controller (208) will generate initial parity values which correlate to the contents of the memory array (200). This parity information is stored within the parity portion of the array (200). After generating the initial parity data, the parity controller (208) occasionally, upon some parity checking event, generates current parity from the data stored within the array (200). This current parity is compared against the parity portion of the array (200) using the parity logic (210). If errors are detected, it is clear that the software/data that was intended to be static and non-changing has experienced a leakage error, soft error event, electrical short, etc.

Abstract: A co-processor (FIG. 2) for performing modular multiplication comprising: means for receiving B and N binary data streams (bstr, nstr); means for receiving a data value A; adder means (Add1, Add2), subtractor means (Sub1, Sub2, Sub3) and multiplier means (Mul1, Mul2) coupled to sequentially process the B and N binary data streams and the data value A to produce a modulo-reduced multiplication value (A*B) mod N; and further including exponentiation means (FIG. 6) comprising: random access memory (E-RAM) for holding an exponent value; parallel-serial interface means for receiving in parallel from the random access memory the exponent value and for producing therefrom a binary data stream E; control means (CONTROL) for receiving the binary data stream E and for initiating a squaring or a multiply operation in dependence on the value of each bit thereof.