Abstract: A method and apparatus for the pipelining of data during direct memory accesses. The processor includes an external bus controller, which receives data transmitted across the external bus from an external device, and forwards the data onto the memory bus for transfer to the memory. Similarly, the bus controller receives data to be written to external device from the memory and transfers it across the external bus to the external device. The bus controller includes logic to detect burst transfers and word alignment to determine the minimum number of words that can be transferred across the memory bus while the data transfer from the external device is ongoing. Therefore, instead of waiting for the entire block of data to be received into the processor before transferring it to the memory, portions of the block transferred, for example, two words at a time, are transferred to the memory, while additional data is being received at the processor.

Abstract: A translation look aside buffer including virtual page table pointer tags provides a system and method for accessing page table entries in page memory of the translation look aside buffer with decrease latencies caused by accesses to increasing levels of page tables during a table walk of the page table. Virtual tags identifying page table pointers at a predetermined level of the page table higher than the initial context level of the page table are included in the tag memory of the translation look aside buffer. These virtual tags provide a pointer which directly points to the page table pointer at that predetermined level of the page table. Therefore, if a TLB miss occurs wherein a tag for a page table entry corresponding to the virtual address is not found, a comparison is performed to determined if a corresponding virtual tag PTP is located in the tag memory.

Abstract: A translation lookaside buffer for use with a virtual memory system including apparatus for storing virtual addresses, apparatus for storing a physical address associated with each of the virtual addresses, some of the physical addresses corresponding to pages in which the information sought by the virtual address resides, and others of the physical addresses corresponding to pages in which the physical address of information sought by the virtual address resides.

Abstract: A translation lookaside buffer for caching virtual addresses from a plurality of sources along with the associated physical addresses which physical addresses must be rapidly accessable and in which virtual addresses may appear simultaneously from two of the sources requiring translation into physical addresses, including a primary cache for storing a plurality of individual virtual addresses and associated physical addresses from all of the plurality of sources, apparatus for storing a single virtual address and its associated physical address from one of the plurality of sources which occurs most often each time a virtual address and an associated physical address from that one of the plurality of sources is referenced in the primary cache, and apparatus for ascertaining whether the virtual address held in the apparatus for storing a single virtual address and an associated physical address is a virtual address sought when an attempt is made to access the primary cache for a virtual address from the one of

Abstract: In the memory access unit of the present invention, the memory request logic is centralized in the memory management unit (MMU). The MMU instructs the MCU, which interfaces directly with the DRAMs, on the type of memory access to perform. By centralizing the memory requests, the MMU is able to maintain an account of each memory access, thereby providing the MMU the means to determine if a memory access fulfills the requirements of a fast page mode access before a request is made to the MCU. The MMU comprises the row address comparator which can execute the row address comparison in parallel with the cache lookup. Therefore, if the cache lookup determines a memory access is required, a specific fast page mode memory access request can be made, without the memory controller incurring the additional delay of checking the row address.

Abstract: A method and apparatus for saving memory space in a buffer whereby the valid bit in the entry of the translation lookaside buffer for a cache memory is collapsed into one of the level bits indicating the length of the virtual address. During the lookup of the translation lookaside buffer, the virtual address in each entry is compared with the virtual address from the CPU if the level/valid bit is set, i.e. the entry is valid. If the level/valid bit is not set, then no compare takes place and the lookup continues to the next entry. The length of the virtual address to be compared is further determined by the status of the remaining level bits.