Abstract: A logic circuit such as a parallel counter comprises logic for generating output bits as elementary symmetric functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.

Abstract: Logic circuit generating four binary outputs as four threshold functions of four binary inputs, including: first, second, third, and fourth threshold functions which are respectively high if at least one, two, three and all of the binary inputs are high; first logic having two logic parts that each include NOR and NAND gates, and having two first-level inputs for receiving the binary inputs and two first-level outputs; and second logic having four second-level outputs, four second-level inputs for receiving second-level binary inputs and connected to the four first-level outputs, NAND gate, first gate generating logical OR combinations and NAND combining the logical OR combination with two other second-level binary inputs, a second gate generating logical OR combinations of two pairs of second-level binary inputs and NAND combining the logical OR combinations, and a NOR gate; wherein one of four binary outputs is generated at each of the four outputs.

Abstract: A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinatins of each bit of a binary number with each other bit of another binary number is generated having a reduced from in order to reduce the steps required in array reduction.

Abstract: A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.

Abstract: A logic circuit such as a parallel counter comprises logic for generating output bits as elementary symmetric functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.

Abstract: Logic circuit generating four binary outputs as four threshold functions of four binary inputs, including: first, second, third, and fourth threshold functions which are respectively high if at least one, two, three and all of the binary inputs are high; first logic having two logic parts that each include NOR and NAND gates, and having two first-level inputs for receiving the binary inputs and two first-level outputs; and second logic having four second-level outputs, four second-level inputs for receiving second-level binary inputs and connected to the four first-level outputs, NAND gate, first gate generating logical OR combinations and NAND combining the logical OR combination with two other second-level binary inputs, a second gate generating logical OR combinations of two pairs of second-level binary inputs and NAND combining the logical OR combinations, and a NOR gate; wherein one of four binary outputs is generated at each of the four outputs.

Abstract: A method and apparatus for state assignment of a logic circuit comprises receiving internal state representations for the logic circuit, determining binary code for the internal state representations by successively dividing the states into disjoint sets of ever decreasing size Each disjoint set of a pair is assigned a one bit at each division step. The division can continue for all bits to be encoded, or the division can be halted and exact encoding used for the encoding of the final number of bits.

Abstract: A logic circuit for performing modular multiplication of a first multi-bit binary number and a second multi-bit binary number is provided. Combination logic combines the second multi-bit binary value with a group of W bits of the first multi-bit binary value every jth input cycle to generate W multi-bit binary combination values every jth input cycle, where the W bits comprise bits jW to (jW+W−1), W>1, j is the cycle index from 0 to k−1, k=N/W, and N is the number of bits of the first multi-bit binary value. Thus in this way a plurality of multi-bit binary combinations are input every cycle in a parallel manner. Accumulation logic holds a plurality of multi-bit binary values accumulated over previous cycles. Reduction logic generates a W bit value &Lgr; in a current cycle for use in the next cycle. A multi-bit modulus binary value is received and combined with the W bit value &Lgr; generated in a current cycle to generate W multi-bit binary values for use in the next cycle.

Abstract: A logic circuit such as a parallel counter comprises logic for generating output bits as elementary symmetric functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.

Abstract: A parallel counter comprises logic for generating output bits as symmetrical functions of the input bits. The parallel counter can be used in a multiplication circuit. A multiplication circuit is also provided in which an array of combinations of each bit of a binary number with each other bit of another binary number is generated having a reduced form in order to reduce the steps required in array reduction.

Abstract: A method and apparatus for state assignment of a logic circuit comprises receiving internal state representations for the logic circuit, determining binary code for the internal state representations by successively dividing the states into disjoint sets of ever decreasing size Each disjoint set of a pair is assigned a one bit at each division step. The division can continue for all bits to be encoded, or the division can be halted and exact encoding used for the encoding of the final number of bits.