Abstract: The expansion of a network by converting the network from a 2-stage folded Clos network to a 3-stage folded Clos network can be cost prohibitive. The system and methods described herein relate to a hybrid network topology. More particularly, the disclosure describes a hybrid topology having internal switches configured in a multidimensional topology configuration. Each of the internal switches are connected to the network hosts with a folded Clos topology.

Abstract: Aspects and implementations of the present disclosure are directed to a network device. The network device includes memory for storing a first dataset comprising first data structures, a second dataset comprising second data structures, and a set of Boolean values. Each first data structure includes an address and a corresponding instruction parameter. Each second data structure includes an address prefix and at least one intermediary value. Each Boolean value corresponds to a respective address prefix and indicates whether the second dataset includes a second data structure with the respective address prefix. The network device is configured to identify a first address and a first address prefix for a first data packet, identify one or more intermediary values for the first address prefix using the set of Boolean values, and identify a packet processing instruction parameter using the one or more identified intermediary values.

Abstract: A network may be configured to route traffic in such a way as to avoid packet loss in an event of link failure. The network may include a plurality of inner switches and a plurality of outer switches coupled to the plurality of inner switches. Each inner switch may be configured to receive traffic, determine whether a link to a next hop for the traffic is down, and forward the traffic to another outer switch if the link to the next hop is down. Each outer switch may be configured to bounce traffic received from the first inner switch to a second inner switch if the traffic is received as a result of determining that the link from the inner switch to the next hop is down. The second inner switch may then deliver the traffic, or further bounce the traffic off another outer switch.

Abstract: Aspects of the invention pertain to routing packets in a computer system while avoiding deadlock. A turn rule is set according to unique identifiers associated with switches in the system. Numeric values of switches in possible turns are compared to determine whether a turn is permissible. The rule applies to all nodes in the system. The rule may be violated when using virtual channels. Here, a violation is permissible when using monotonically increasing virtual channel numbers or monotonically decreasing virtual channel numbers. Alternatively, the violations of the turn rule may be allowed if they force a packet to change to a later virtual channel in some fixed ordering of virtual channels. Deadlock can thus be avoided in many different types of architectures, including mesh, torus, butterfly and flattened butterfly configurations.

Abstract: Energy proportional solutions are provided for computer networks such as datacenters. Congestion sensing heuristics are used to adaptively route traffic across links. Traffic intensity is sensed and links are dynamically activated as they are needed. As the offered load is decreased, the lower channel utilization is sensed and the link speed is reduced to save power. Flattened butterfly topologies can be used in a further power saving approach. Switch mechanisms are exploit the topology's capabilities by reconfiguring link speeds on-the-fly to match bandwidth and power with the traffic demand. For instance, the system may estimate the future bandwidth needs of each link and reconfigure its data rate to meet those requirements while consuming less power. In one configuration, a mechanism is provided where the switch tracks the utilization of each of its links over an epoch, and then makes an adjustment at the end of the epoch.

Abstract: Adaptive packet routing is employed in a multiprocessor network configuration such as an InfiniBand switch architecture. Packets are routed from host to host through one or more switches. Upon receipt of a packet at a switch, the packet header is inspected to determine the destination host. A destination field in the header is used to index into a lookup table or other memory, which produces a route type and an output port grouping. Depending on the route type, one or more primary and secondary output port candidates are identified. An output port arbitration module chooses an output port from which to send a given packet, using congestion sensing inputs for the specified ports. A heuristic may include the congestion information that is provided to the arbitration module. Switching may be performed among minimal or non-minimal routes along each hop in the path, depending upon link and packet injection information.

Abstract: Energy proportional solutions are provided for computer networks such as datacenters. Congestion sensing heuristics are used to adaptively route traffic across links. Traffic intensity is sensed and links are dynamically activated as they are needed. As the offered load is decreased, the lower channel utilization is sensed and the link speed is reduced to save power. Flattened butterfly topologies can be used in a further power saving approach. Switch mechanisms are exploit the topology's capabilities by reconfiguring link speeds on-the-fly to match bandwidth and power with the traffic demand. For instance, the system may estimate the future bandwidth needs of each link and reconfigure its data rate to meet those requirements while consuming less power. In one configuration, a mechanism is provided where the switch tracks the utilization of each of its links over an epoch, and then makes an adjustment at the end of the epoch.

Abstract: Aspects of the invention pertain to routing packets in a computer system while avoiding deadlock. A turn rule is set according to unique identifiers associated with switches in the system. Numeric values of switches in possible turns are compared to determine whether a turn is permissible. The rule applies to all nodes in the system. The rule may be violated when using virtual channels. Here, a violation is permissible when using monotonically increasing virtual channel numbers or monotonically decreasing virtual channel numbers. Alternatively, the violations of the turn rule may be allowed if they force a packet to change to a later virtual channel in some fixed ordering of virtual channels. Deadlock can thus be avoided in many different types of architectures, including mesh, torus, butterfly and flattened butterfly configurations.

Abstract: Aspects of the invention pertain to routing packets in a computer system while avoiding deadlock. A turn rule is set according to unique identifiers associated with switches in the system. Numeric values of switches in possible turns are compared to determine whether a turn is permissible. The rule applies to all nodes in the system. The rule may be violated when using virtual channels. Here, a violation is permissible when using monotonically increasing virtual channel numbers or monotonically decreasing virtual channel numbers. Alternatively, the violations of the turn rule may be allowed if they force a packet to change to a later virtual channel in some fixed ordering of virtual channels. Deadlock can thus be avoided in many different types of architectures, including mesh, torus, butterfly and flattened butterfly configurations.

Abstract: Adaptive packet routing is employed in a multiprocessor network configuration such as an InfiniBand switch architecture. Packets are routed from host to host through one or more switches. Upon receipt of a packet at a switch, the packet header is inspected to determine the destination host. A destination field in the header is used to index into a lookup table or other memory, which produces a route type and an output port grouping. Depending on the route type, one or more primary and secondary output port candidates are identified. An output port arbitration module chooses an output port from which to send a given packet, using congestion sensing inputs for the specified ports. A heuristic may include the congestion information that is provided to the arbitration module. Switching may be performed among minimal or non-minimal routes along each hop in the path, depending upon link and packet injection information.

Abstract: Aspects of the invention pertain to routing packets in a computer system while avoiding deadlock. A turn rule is set according to unique identifiers associated with switches in the system. Numeric values of switches in possible turns are compared to determine whether a turn is permissible. The rule applies to all nodes in the system. The rule may be violated when using virtual channels. Here, a violation is permissible when using monotonically increasing virtual channel numbers or monotonically decreasing virtual channel numbers. Alternatively, the violations of the turn rule may be allowed if they force a packet to change to a later virtual channel in some fixed ordering of virtual channels. Deadlock can thus be avoided in many different types of architectures, including mesh, torus, butterfly and flattened butterfly configurations.

Abstract: Aspects of the invention pertain to routing packets in a computer system while avoiding deadlock. A turn rule is set according to unique identifiers associated with switches in the system. Numeric values of switches in possible turns are compared to determine whether a turn is permissible. The rule applies to all nodes in the system. The rule may be violated when using virtual channels. Here, a violation is permissible when using monotonically increasing virtual channel numbers or monotonically decreasing virtual channel numbers. Alternatively, the violations of the turn rule may be allowed if they force a packet to change to a later virtual channel in some fixed ordering of virtual channels. Deadlock can thus be avoided in many different types of architectures, including mesh, torus, butterfly and flattened butterfly configurations.

Abstract: Aspects of the invention pertain to routing packets in a computer system while avoiding deadlock. A turn rule is set according to unique identifiers associated with switches in the system. Numeric values of switches in possible turns are compared to determine whether a turn is permissible. The rule applies to all nodes in the system. The rule may be violated when using virtual channels. Here, a violation is permissible when using monotonically increasing virtual channel numbers or monotonically decreasing virtual channel numbers. Alternatively, the violations of the turn rule may be allowed if they force a packet to change to a later virtual channel in some fixed ordering of virtual channels. Deadlock can thus be avoided in many different types of architectures, including mesh, torus, butterfly and flattened butterfly configurations.

Abstract: A method and system for operating a computing system having multiple processing units. According to a new machine instruction, called the iota instruction, the computing system operates on a vector of mask bits to generate an iota vector having a sequence of values. In one form, each value of the iota vector is a sum of a series of the lower order mask bits up to and including the mask bit corresponding to the entry in the iota vector. In another form, each entry in the iota vector is a sum of a series of lower order mask bits but does not include the mask bit corresponding to the particular entry in the iota vector. In order to calculate the iota vector, the multiple processing units of the present invention communicate the mask bits to the other processing units. Advantages of the present invention include the vectorization of software loops having certain data hazards that prevented conventional compilers from vectorizing the software.