Abstract: A circuit and methodology for higher radix multiplication with improved partial product generation. The invention relates to the design of a high precision multiplier for an arithmetic unit of a digital processor.

Abstract: Apparatus and method for performing IEEE-rounded floating-point division utilizing Goldschmidt's algorithm. The use of Newton's method in computing quotients requires two multiplication operations, which must be performed sequentially, and therefore incurs waiting delays and decreases throughput. Goldschmidt's algorithm uses two multiplication operations which are independent and therefore may be performed simultaneously via pipelining. Unfortunately, current error estimates for Goldschmidt's algorithm are imprecise, requiring high-precision multiplication operations for stability, thereby reducing the advantages of the pipelining. A new error analysis provides improved methods for estimating the error in the Goldschmidt algorithm iterations, resulting in reductions in the hardware, improved pipeline organization, reducing the number and length of clock cycles, reducing latency, and increasing throughput.

Abstract: An IEEE floating-point adder (FP-adder) design. The adder accepts normalized numbers, supports all four IEEE rounding modes, and outputs the correctly normalized rounded sum/difference in the format required by the IEEE Standard. The latency of the design for double precision is roughly 24 logic levels, not including delays of latches between pipeline stages. Moreover, the design can be easily partitioned into two stages comprised of twelve logic levels each, and hence, can be used with clock periods that allow for twelve logic levels between latches. The FP-adder design achieves a low latency by combining various optimization techniques, including a non-standard separation into two paths, a simple rounding algorithm, unifying rounding cases for addition and subtraction, sign-magnitude computation of a difference based on one's complement subtraction, compound adders, and fast circuits for approximate counting of leading zeros from borrow-save representation.

Abstract: A method and apparatus for improving the efficiency of hardware-based binary multiplication. By using radix-32 and radix-256 multipliers where each radix-32 digit is represented by two radix-7 digits and each radix-256 digit is represented by three radix-11 digits, the digit magnitudes are in power of two, which simplifies the implementation of the partial product generation. The partial products depending on multiples of the radices 7 or 11 can be separately accumulated, with multiplication by the radix a pre- or post-computation option.