Abstract: A process to form a HEMT can have a gate electrode layer that initially has a plurality of spaced-apart doped regions. In an embodiment, any of the spaced-apart doped regions can be formed by depositing or implanting p-type dopant atoms. After patterning, the gate electrode can include an n-type doped region over the p-type doped region. In another embodiment a barrier layer can underlie the gate electrode and include a lower film with a higher Al content and thinner than an upper film. In a further embodiment, a silicon nitride layer can be formed over the gate electrode layer and can help to provide Si atoms for the n-type doped region and increase a Mg:H ratio within the gate electrode. The HEMT can have good turn-on characteristics, low gate leakage when in the on-state, and better time-dependent breakdown as compared to a conventional HEMT.

Abstract: In a general aspect, a semiconductor device assembly includes a first portion of a semiconductor substrate; a second portion of the semiconductor substrate, and a semiconductor device layer disposed on the first portion of the semiconductor substrate and the second portion of the semiconductor substrate. The semiconductor device layer includes a first semiconductor device disposed on the first portion of the semiconductor substrate, and a second semiconductor device disposed on the second portion of the semiconductor substrate. The assembly also includes an isolation trench defined in the semiconductor substrate that has a dielectric material disposed therein. The isolation trench is disposed between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate, and electrically isolates the first portion of the semiconductor substrate from the second portion of the semiconductor substrate. The semiconductor device layer excludes the isolation trench.

Abstract: An accumulation MOSFET includes a plurality of device cells. Each device cell includes a mesa adjoining a vertical trench is disposed in a doped semiconductor substrate. The mesa has a top mesa portion disposed on a bottom mesa portion. The top mesa portion has a width that is narrower than a width of the bottom mesa portion. The vertical trench adjoining the mesa has a top trench portion and a bottom trench portion. The top trench portion has a width that is wider than a width of the bottom trench portion. A dielectric is disposed on a sidewall of the vertical trench. A gate electrode disposed in the top trench portion forms an accumulation channel region in the top mesa portion and a shield electrode disposed in the bottom trench portion forms a depletion drift region in the bottom mesa portion.

Abstract: In a general aspect, a semiconductor device assembly can include a semiconductor substrate that excludes a buried oxide layer. The semiconductor device assembly can also include a first semiconductor device stack disposed on a first portion of the semiconductor substrate, and a second semiconductor device stack disposed on a second portion of the semiconductor substrate. The semiconductor device assembly can further include an isolation trench having a dielectric material disposed therein, the isolation trench being disposed between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate. The isolation trench can electrically isolate the first portion of the semiconductor substrate from the second portion of the semiconductor substrate.

Abstract: An electronic device can include a HEMT. In an embodiment, a gate electrode, a drain electrode, and an access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode. A lower dielectric film can overlie a portion of the access region, and an upper dielectric region can overlie another portion of the access region. In another embodiment, a dielectric film can have a relatively positive or negative charge and a varying thickness. In a further embodiment, the HEMT can include a gate electrode; a dielectric film overlying the gate electrode and defining openings to the gate electrode, wherein a portion of the dielectric film is disposed between the openings; and a gate interconnect extending into the openings of the dielectric film and contacting the gate electrode and the portion of the dielectric film.

Abstract: A High Electron Mobility Transistor (HEMT) includes a source, a drain, a channel layer extending between the source and the drain, a barrier layer formed in contact with the channel layer, and extending between the source and the drain, and a gate formed in contact with, and covering at least a portion of, the barrier layer. The gate has gate edge portions and a gate central portion, and dielectric spacers may be formed over the gate edge portions, with the dielectric spacers having a first width therebetween proximal to the gate, and a second width therebetween distal from the gate, where the second width is longer than the first width.

Abstract: Diodes, transistors, and other devices having a class IV channel region and a class III-V drift region are described. The class IV channel region, such as a Si channel region, is able to provide all associated advantages, such as ease of manufacturing of many different types of devices, using cost-effective materials and techniques. Meanwhile, the III-V drift region provides substantially lower Ron_sp than a conventional class IV drift region, and substantially enhances the operational behaviors of resulting devices, without sacrificing other parameters, such as size or breakdown voltage.

Abstract: High Electron Mobility Transistors (HEMTs) are described with a circular gate, with a drain region disposed within the circular gates and circular source region disposed around the circular gates. The circular gate and the circular source region may form complete circles.

Abstract: A process to form a HEMT can have a gate electrode layer that initially has a plurality of spaced-apart doped regions. In an embodiment, any of the spaced-apart doped regions can be formed by depositing or implanting p-type dopant atoms. After patterning, the gate electrode can include an n-type doped region over the p-type doped region. In another embodiment a barrier layer can underlie the gate electrode and include a lower film with a higher Al content and thinner than an upper film. In a further embodiment, a silicon nitride layer can be formed over the gate electrode layer and can help to provide Si atoms for the n-type doped region and increase a Mg:H ratio within the gate electrode. The HEMT can have good turn-on characteristics, low gate leakage when in the on-state, and better time-dependent breakdown as compared to a conventional HEMT.

Abstract: In a general aspect, a transistor can include a fin having a proximal end and a distal end. The fin can include a dielectric portion longitudinally extending between the proximal end and the distal end, and a semiconductor layer disposed on the dielectric portion. The semiconductor layer can longitudinally extend between the proximal end and the distal end. The transistor can further include a source region disposed at the proximal end of the fin, and a drain region disposed at the distal end of the fin. The transistor can also include a gate dielectric layer disposed on a channel region of the semiconductor layer. The channel region can be disposed between the gate dielectric layer and the dielectric portion. The channel region can be longitudinally disposed between the source region and the drain region. The transistor can further include a conductive gate electrode disposed on the gate dielectric layer.

Abstract: An electronic device including a transistor structure, and a process of forming the electronic device can include providing a workpiece including a substrate, a first layer, and a channel layer including a compound semiconductor material; and implanting a species into the workpiece such that the projected range extends at least into the channel and first layers, and the implant is performed into an area corresponding to at least a source region of the transistor structure. In an embodiment, the area corresponds to substantially all area occupied by the transistor structure. In another embodiment, the implant can form crystal defects within layers between the substrate and source, gate, and drain electrodes. The crystal defects may allow resistive coupling between the substrate and the channel structure within the transistor structure. The resistive coupling allows for better dynamic on-state resistance and potentially other electrical properties.

Abstract: An Enhancement Mode (e-mode) Metal Insulator Semiconductor (MIS) High Electron Mobility Transistor (HEMT), or EMISHEMT, with GaN channel regrowth under a gate area, is described. The EMISHEMT with GaN channel regrowth under a gate area provides a normally-off device with a suitably high and stable threshold voltage, while providing a low gate leakage current. A channel layer provides a 2DEG and associated low on-resistance, while a channel-material layer extends through an etched recess and into the channel layer, and disrupts the 2DEG locally to enable the normally-off operation.

Abstract: In an embodiment, a HEMT is formed to have a main transistor having a main active area and a sense transistor having a sense active area. An embodiment may include that the main active area is isolated from the sense active area.

Abstract: In a general aspect, a semiconductor device assembly can include a semiconductor substrate that excludes a buried oxide layer. The semiconductor device assembly can also include a first semiconductor device stack disposed on a first portion of the semiconductor substrate, and a second semiconductor device stack disposed on a second portion of the semiconductor substrate. The semiconductor device assembly can further include an isolation trench having a dielectric material disposed therein, the isolation trench being disposed between the first portion of the semiconductor substrate and the second portion of the semiconductor substrate. The isolation trench can electrically isolate the first portion of the semiconductor substrate from the second portion of the semiconductor substrate.

Abstract: An Enhancement Mode (e-mode) Metal Insulator Semiconductor (MIS) High Electron Mobility Transistor (HEMT), or EMISHEMT, with GaN channel regrowth under a gate area, is described. The EMISHEMT with GaN channel regrowth under a gate area provides a normally-off device with a suitably high and stable threshold voltage, while providing a low gate leakage current. A channel layer provides a 2DEG and associated low on-resistance, while a channel-material layer extends through an etched recess and into the channel layer, and disrupts the 2DEG locally to enable the normally-off operation.

Abstract: An opto-electronic High Electron Mobility Transistor (HEMT) may include a current channel including a two-dimensional electron gas (2DEG). The opto-electronic HEMT may further include a photoelectric bipolar transistor embedded within at least one of a source and a drain of the HEMT, the photoelectric bipolar transistor being in series with the current channel of the HEMT.

Abstract: An opto-electronic High Electron Mobility Transistor (HEMT) may include a current channel including a two-dimensional electron gas (2DEG). The opto-electronic HEMT may further include a photoelectric bipolar transistor embedded within at least one of a source and a drain of the HEMT, the photoelectric bipolar transistor being in series with the current channel of the HEMT.

Abstract: An electronic device can include a HEMT. In an embodiment, a gate electrode, a drain electrode, and an access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode. A lower dielectric film can overlie a portion of the access region, and an upper dielectric region can overlie another portion of the access region. In another embodiment, a dielectric film can have a relatively positive or negative charge and a varying thickness. In a further embodiment, the HEMT can include a gate electrode; a dielectric film overlying the gate electrode and defining openings to the gate electrode, wherein a portion of the dielectric film is disposed between the openings; and a gate interconnect extending into the openings of the dielectric film and contacting the gate electrode and the portion of the dielectric film.

Abstract: An electronic device can include a HEMT. In an embodiment, a gate electrode, a drain electrode, and an access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode. A lower dielectric film can overlie a portion of the access region, and an upper dielectric region can overlie another portion of the access region. In another embodiment, a dielectric film can have a relatively positive or negative charge and a varying thickness. In a further embodiment, the HEMT can include a gate electrode; a dielectric film overlying the gate electrode and defining openings to the gate electrode, wherein a portion of the dielectric film is disposed between the openings; and a gate interconnect extending into the openings of the dielectric film and contacting the gate electrode and the portion of the dielectric film.

Abstract: An electronic device can include a HEMT. In an embodiment, a gate electrode, a drain electrode, and an access region including a first portion closer to the gate electrode and a second portion closer to the drain electrode. A lower dielectric film can overlie a portion of the access region, and an upper dielectric region can overlie another portion of the access region. In another embodiment, a dielectric film can have a relatively positive or negative charge and a varying thickness. In a further embodiment, the HEMT can include a gate electrode; a dielectric film overlying the gate electrode and defining openings to the gate electrode, wherein a portion of the dielectric film is disposed between the openings; and a gate interconnect extending into the openings of the dielectric film and contacting the gate electrode and the portion of the dielectric film.