Patents by Inventor Peter Moens
Peter Moens has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140097489Abstract: In one embodiment, a semiconductor device has a superjunction structure formed adjoining a low-doped n-type region. A low-doped p-type region is formed adjoining the superjunction structure above the low-doped n-type region and is configured to improve Eas characteristics. A body region is formed adjacent the low-doped p-type region and a control electrode structure is formed adjacent the body region for controlling a channel region within the body region.Type: ApplicationFiled: September 12, 2013Publication date: April 10, 2014Applicant: Semiconductor Components Industries, LLCInventors: Jaume Roig-Guitart, Peter Moens, Piet Vanmeerbeek
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Patent number: 8648398Abstract: An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.Type: GrantFiled: September 26, 2012Date of Patent: February 11, 2014Assignee: Semiconductor Components Industries, LLCInventors: Jaume Roig-Guitart, Peter Moens, Marnix Tack
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Publication number: 20140006053Abstract: A computerized method for administration of a health care system, comprising, providing a central computer system having remote access capability to one or more participants via a remote computer link, assessing the participants health care needs through one or more query instructions utilizing said central computer system to collect the participants health care information, and aggregating the health care information into a unique participant ID.Type: ApplicationFiled: December 20, 2012Publication date: January 2, 2014Inventors: David MOEN, Peter MOEN
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Publication number: 20130020637Abstract: An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.Type: ApplicationFiled: September 26, 2012Publication date: January 24, 2013Inventors: Juame Roig-Guitart, Peter Moens, Marnix Tack
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Patent number: 8298889Abstract: An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.Type: GrantFiled: December 10, 2008Date of Patent: October 30, 2012Assignee: Semiconductor Components Industries, LLCInventors: Jaume Roig-Guitart, Peter Moens, Marnix Tack
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Patent number: 8299528Abstract: An electronic device can include a first well region of a first conductivity-type and a second well region of a second conductivity-type and abutting the first well region. The first conductivity-type and the second conductivity type can be opposite conductivity types. In an embodiment, an insulator region can extend into the first well region, wherein the insulator region and the first well region abut and define an interface, and, from a top view, the insulator region can include a first feature extending toward the first interface, and the insulator region can define a first space bounded by the first feature, wherein a dimension from a portion of the first feature closest to the first interface is at least zero. A gate structure can overlie an interface between the first and second well regions.Type: GrantFiled: December 31, 2009Date of Patent: October 30, 2012Assignee: Semiconductor Components Industries, LLCInventors: Jaume Roig-Guitart, Peter Moens
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Publication number: 20120187526Abstract: At least one exemplary embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several conductivity layers and a buffer layer.Type: ApplicationFiled: January 21, 2011Publication date: July 26, 2012Inventors: Jaume Roig-Guitart, Zia Hossain, Peter Moens
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Publication number: 20120187527Abstract: At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.Type: ApplicationFiled: September 7, 2011Publication date: July 26, 2012Inventors: Jaume Roig Guitart, Peter Moens, Zia Hossain
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Patent number: 8115273Abstract: A integrated semiconductor device has a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type over the first layer, a third semiconductor layer of a second conductivity type over the second layer, an isolation trench extending through the entire depth of the second and third layers into the first layer, and a first region of the second conductivity type located next to the isolation trench and extending from an interface between the second and third layers, along an interface between the second layer and the isolation trench. This first region can help reduce a concentration of field lines where the isolation trench meets the interface of the second and third layers, and hence provide a better reverse breakdown characteristic.Type: GrantFiled: June 27, 2008Date of Patent: February 14, 2012Assignee: Semiconductor Components Industries, LLCInventors: Peter Moens, Filip Bauwens, Joris Baele
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Patent number: 7989886Abstract: Manufacturing a power transistor by forming a gate structure on a first layer, forming a trench in the first layer, self aligned with the gate structure, and forming part of the transistor in the trench. By forming a spacer next to the gate, the spacer and gate can be used as a mask when forming the trench, to allow space for a source region next to the gate. The self-aligning rather than forming the gate after the trench means the alignment is more accurate, allowing size reduction. Another aspect involves forming a trench in a first layer, filling the trench, forming a second layer on either side of the trench with lateral overgrowth over the trench, and forming a source region in the second layer to overlap the trench. This overlap can enable the chip area to be reduced.Type: GrantFiled: September 15, 2009Date of Patent: August 2, 2011Assignee: Semiconductor Components Industries, LLCInventors: Peter Moens, Marnix Tack
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Publication number: 20110156141Abstract: An electronic device can include a first well region of a first conductivity-type and a second well region of a second conductivity-type and abutting the first well region. The first conductivity-type and the second conductivity type can be opposite conductivity types. In an embodiment, an insulator region can extend into the first well region, wherein the insulator region and the first well region abut and define an interface, and, from a top view, the insulator region can include a first feature extending toward the first interface, and the insulator region can define a first space bounded by the first feature, wherein a dimension from a portion of the first feature closest to the first interface is at least zero. A gate structure can overlie an interface between the first and second well regions.Type: ApplicationFiled: December 31, 2009Publication date: June 30, 2011Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jaume Roig-Guitart, Peter Moens
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Patent number: 7915155Abstract: Semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other pails of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.Type: GrantFiled: January 4, 2010Date of Patent: March 29, 2011Assignee: Semiconductor Components Industries, L.L.C.Inventors: Peter Moens, Marnix Tack, Sylvie Boonen, Paul Colson
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Patent number: 7804670Abstract: A circuit for protecting a semiconductor from electrostatic discharge events includes a Zener diode (21) in series with a resistor (22) between a power line HV VDD and a ground fine HV VSS. A gate of a DMOS device (23) is connected to a node between the diode and the resistor. The drain and source of the DMOS are connected between the power lines. During an ESD event, the gate voltage of the DMOS increases and the ESD current will be discharged through the DMOS to ground. When the current exceeds the capacity of the channel of the DMOS, a parasitic bipolar transistor or transistors associated with the DMOS device acts in a controlled snapback to discharge the current to ground. The use of a vertical DMOS (VDMOS) instead of a lateral DMOS (LDMOS), can reduce the area of the device and improve the protection.Type: GrantFiled: January 7, 2005Date of Patent: September 28, 2010Assignee: Semiconductor Components Industries, L.L.C.Inventors: Koen Reynders, Peter Moens
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Publication number: 20100140698Abstract: An electronic device can include a first layer having a primary surface, a well region lying adjacent to the primary surface, and a buried doped region spaced apart from the primary surface and the well region. The electronic device can also include a trench extending towards the buried doped region, wherein the trench has a sidewall, and a sidewall doped region along the sidewall of the trench, wherein the sidewall doped region extends to a depth deeper than the well region. The first layer and the buried region have a first conductivity type, and the well region has a second conductivity type opposite that of the first conductivity type. The electronic device can include a conductive structure within the trench, wherein the conductive structure is electrically connected to the buried doped region and is electrically insulated from the sidewall doped region. Processes for forming the electronic device are also described.Type: ApplicationFiled: December 10, 2008Publication date: June 10, 2010Inventors: Jaume Roig-Guitart, Peter Moens, Marnix Tack
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Patent number: 7723800Abstract: An integrated power semiconductor device has an isolation structure having two or more isolation trenches, and one or more regions in between the isolation trenches, and a bias arrangement coupled to the regions to divide a voltage across the isolation structure between the isolation trenches. By dividing the voltage, the reverse breakdown voltage characteristics such as voltage level, reliability and stability can be improved for a given area of device, or for a given complexity of device, and avalanche breakdown at weaknesses in isolation structures can be reduced or avoided.Type: GrantFiled: May 23, 2008Date of Patent: May 25, 2010Assignee: Semiconductor Components Industries, LLCInventors: Peter Moens, Bart Desoete
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Patent number: 7709889Abstract: The present invention provides a semiconductor device (20) comprising a trench (5) formed in a semiconductor substrate formed of a stack (4) of layers (1,2,3), a layer (6) of a first, grown dielectric material covering sidewalls and bottom of the trench (5), the layer (6) including one or more notches (13) at the bottom of the trench (5) and one or more spacers (14) formed of a second, deposited dielectric material to fill the one or more notches (13) in the layer (6) formed of the first, grown dielectric material. The semiconductor device (20) according to the present invention shows improved breakdown voltage and on-resistance. The present invention furthermore provides a method for the manufacturing of such semiconductor devices (20).Type: GrantFiled: July 26, 2007Date of Patent: May 4, 2010Assignee: Semiconductor Components Industries, L.L.C.Inventors: Peter Moens, Filip Bauwens, Joris Baele, Marnix Tack
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Publication number: 20100105188Abstract: Semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other pails of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.Type: ApplicationFiled: January 4, 2010Publication date: April 29, 2010Inventors: Peter MOENS, Marnix Tack, Sylvie Boonen, Paul Colson
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Publication number: 20100065908Abstract: Manufacturing a power transistor by forming a gate structure on a first layer, forming a trench in the first layer, self aligned with the gate structure, and forming part of the transistor in the trench. By forming a spacer next to the gate, the spacer and gate can be used as a mask when forming the trench, to allow space for a source region next to the gate. The self-aligning rather than forming the gate after the trench means the alignment is more accurate, allowing size reduction. Another aspect involves forming a trench in a first layer, filling the trench, forming a second layer on either side of the trench with lateral overgrowth over the trench, and forming a source region in the second layer to overlap the trench. This overlap can enable the chip area to be reduced.Type: ApplicationFiled: September 15, 2009Publication date: March 18, 2010Inventors: Peter MOENS, Marnix Tack
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Patent number: 7667270Abstract: A semiconductor device has a substrate (50), a buried layer (55), an active area extending from a surface contact to the buried layer, an insulator (130) in a first trench extending towards the buried layer, to isolate the active area, and a second insulator (130) in a second deep trench and extending through the buried layer to isolate the buried layer and the active area from other parts of the substrate. This double trench can help reduce the area needed for the electrical isolation between the active device and the other devices. Such reduction in area can enable greater integration or more cells in a multi cell super-MOS device, and so improve performance parameters such as Ron. The double trench can be manufactured using a first mask to etch both trenches at the same time, and subsequently using a second mask to etch the second deep trench deeper.Type: GrantFiled: April 7, 2006Date of Patent: February 23, 2010Assignee: Semiconductor Components Industries LLCInventors: Peter Moens, Marnix Tack, Sylvie Boonen, Paul Colson
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Publication number: 20090268357Abstract: A circuit for protecting a semiconductor from electrostatic discharge events includes a Zener diode (21) in series with a resistor (22) between a power line HV VDD and a ground fine HV VSS. A gate of a DMOS device (23) is connected to a node between the diode and the resistor. The drain and source of the DMOS are connected between the power lines. During an ESD event, the gate voltage of the DMOS increases and the ESD current will be discharged through the DMOS to ground. When the current exceeds the capacity of the channel of the DMOS, a parasitic bipolar transistor or transistors associated with the DMOS device acts in a controlled snapback to discharge the current to ground. The use of a vertical DMOS (VDMOS) instead of a lateral DMOS (LDMOS), can reduce the area of the device and improve the protection.Type: ApplicationFiled: January 7, 2005Publication date: October 29, 2009Inventors: Koen Reynders, Peter Moens