Abstract: A circuit package includes a substrate formed using a plurality of layers, the substrate having a first surface and a second surface, at least some of the plurality of layers being electrically interconnected by a via; and at least one standard surface-mount capacitive element electrically coupled to at least one surface of the substrate, thereby allowing electrical and mechanical access to the first surface and the second surface, the at least one standard surface-mount capacitive element located to prevent the passage of a direct current (DC) signal through the circuit package.

Abstract: A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.

Abstract: A method for routing vias in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with an internal bond surface having a plurality of internal bond pads and an external bond surface with a plurality of external bond pads. A plurality of power vias and ground vias may be routed from a first redistribution layer between the internal bond surface and the external bond surface to a second redistribution layer between the first redistribution layer and the external bond surface based on a via pattern. The via pattern may comprise routing a power via and a ground via adjacent one another spaced apart at a distance that is substantially equal to a minimum routing pitch associated with the multilayer substrate.

Abstract: A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.

Abstract: A method for routing signals in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with at least one differential signal line pair aligned along a common plane that is substantially transverse to a top surface of the multilayer substrate, jogging a first differential signal line associated with a differential signal line pair at a first redistribution layer in a direction along the common plane, and jogging a second differential signal line associated with the differential signal line pair at a second redistribution layer along the common plane in a same direction as the first differential signal line to provide a substantially balanced differential signal line pair.