Patents by Inventor Peter Moll
Peter Moll has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11844864Abstract: A method for preparing granules. A slurry containing solid API powder particles dispersed in a liquid is prepared. The slurry is fed to a granulator and mixed with a dry base powder within the granulator in order to produce a slurry/base powder mixture. The slurry/base powder mixture produced within the granulator is dried in order to obtain granules containing the solid API particles and the base powder.Type: GrantFiled: August 30, 2018Date of Patent: December 19, 2023Assignee: Novartis AGInventors: Markus Krumme, Hans De Waard, Klaus-Peter Moll, Adrian Schmidt, Julien Taillemite
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Publication number: 20230355582Abstract: Drug products in the form of modified release formulations comprising the drug substance (-)-(3aR,45,7aR)-4-Hydroxy-4m-tolylethynyl-octahydro-indole-1-carboxylic acid methyl ester (AFQ056), as well as processes for making such drug products are provided. The drug products are useful in treating patients with Parkinson's disease and exhibiting L-dopa induced dyskinesia.Type: ApplicationFiled: July 20, 2023Publication date: November 9, 2023Applicant: NOVARTIS AGInventors: Bruno GALLI, Jean-Marie GLANTZMANN, Arnaud GRANDEURY, Klaus-Peter MOLL, Martin MUELLER-ZSIGMONDY, Karsten PUTZBACH, Dirk SPICKERMANN, Hubert THOMA, Mike UFER
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Publication number: 20210069114Abstract: A method for preparing granules a slurry containing solid API powder particles dispersed in a liquid is prepared. The slurry is fed to a granulator and mixed with a dry base powder within the granulator in order to produce a slurry/base powder mixture. The slurry/base powder mixture produced within the granulator is dried in order to obtain granules containing the solid API particles and the base powder.Type: ApplicationFiled: August 30, 2018Publication date: March 11, 2021Inventors: Markus KRUMME, Hans DE WAARD, Klaus-Peter MOLL, Adrian ACHMIDT, Julien TAILLEMITE
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Publication number: 20210069150Abstract: Drug products in the form of modified release formulations comprising the drug substance (?)-(3aR,4S,7aR)-4-Hydroxy-4m-tolylethynyl-octahydro-indole-1-carboxylic acid methyl ester (AFQ056), as well as processes for making such drug products are provided. The drug products are useful in treating patients with Parkinson's disease and exhibiting L-dopa induced dyskinesia.Type: ApplicationFiled: June 10, 2020Publication date: March 11, 2021Inventors: Bruno GALLI, Jean-Marie GLANTZMANN, Arnaud GRANDEURY, Klaus-Peter MOLL, Martin MUELLER- ZSIGMONDY, Karsten PUTZBACH, Dirk SPICKERMANN, Hubert THOMA, Mike UFER
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Publication number: 20200222325Abstract: In a method for preparing at least partially dried granules, an API, a base powder, and a granulation liquid are fed to a granulator. The API, the base powder and the granulation liquid are mixed within the granulator to produce an API/base powder/granulation liquid mixture. This liquid mixture within the granulator is heated to a heating temperature (TH) that exceeds an evaporation temperature (TE) of the granulation liquid contained in an API/base powder/granulation liquid mixture to allow at least a part of the granulation liquid contained in the API/base powder/granulation liquid mixture to evaporate in order to obtain at least partially dried granules containing at least the API and the base powder. The at least partially dried granules are discharged from the granulator.Type: ApplicationFiled: August 30, 2018Publication date: July 16, 2020Inventors: Markus KRUMME, Hans DE WAARD, Klaus-Peter MOLL, Adrian SCHMIDT, Frantz ELBAZ, Peter KLEINEBUDDE
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Patent number: 10395981Abstract: The present disclosure relates to semiconductor devices and manufacturing techniques in which topography-related contact failures may be reduced by providing a dielectric fill material in a late manufacturing stage. In sophisticated semiconductor devices, the material loss in the trench isolation regions may result in significant contact failures, which may be reduced by levelling the device topography, thereby tolerating a significant lateral overlap of contact elements with trench isolation regions.Type: GrantFiled: October 25, 2017Date of Patent: August 27, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Hans-Peter Moll, Jeremy Austin Wahl
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Publication number: 20190122921Abstract: The present disclosure relates to semiconductor devices and manufacturing techniques in which topography-related contact failures may be reduced by providing a dielectric fill material in a late manufacturing stage. In sophisticated semiconductor devices, the material loss in the trench isolation regions may result in significant contact failures, which may be reduced by levelling the device topography, thereby tolerating a significant lateral overlap of contact elements with trench isolation regions.Type: ApplicationFiled: October 25, 2017Publication date: April 25, 2019Inventors: Hans-Peter Moll, Jeremy Austin Wahl
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Patent number: 10224251Abstract: When forming sophisticated semiconductor devices requiring resistors based on polysilicon material having non-silicided portions, the respective cap material for defining the silicided portions may be omitted during the process sequence, for instance, by using a patterned liner material or by applying a process strategy for removing the metal material from resistor areas that may not receive a corresponding metal silicide. By implementing the corresponding process strategies, semiconductor devices may be obtained with reduced probability of contact failures, with superior performance due to relaxing surface topography upon forming the contact level, and/or with increased robustness with respect to contact punch-through.Type: GrantFiled: August 2, 2017Date of Patent: March 5, 2019Assignee: GLOBALFOUNDRIES Inc.Inventors: Hans-Peter Moll, Peter Baars, Gunter Grasshoff
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Publication number: 20190043764Abstract: When forming sophisticated semiconductor devices requiring resistors based on polysilicon material having non-silicided portions, the respective cap material for defining the silicided portions may be omitted during the process sequence, for instance, by using a patterned liner material or by applying a process strategy for removing the metal material from resistor areas that may not receive a corresponding metal silicide. By implementing the corresponding process strategies, semiconductor devices may be obtained with reduced probability of contact failures, with superior performance due to relaxing surface topography upon forming the contact level, and/or with increased robustness with respect to contact punch-through.Type: ApplicationFiled: August 2, 2017Publication date: February 7, 2019Inventors: Hans-Peter Moll, Peter Baars, Gunter Grasshoff
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Patent number: 10115621Abstract: Methods for in-die overlay reticle measurement and the resulting devices are disclosed. Embodiments include providing parallel structures in a first layer on a substrate; determining measurement sites, in a second layer above the first layer, void of active integrated circuit elements; forming overlay trenches, in the measurement sites and parallel to the structures, exposing sections of the structures, wherein each overlay trench is aligned over a structure and over spaces between the structure and adjacent structures; determining a trench center-of-gravity of an overlay trench; determining a structure center-of-gravity of a structure exposed in the overlay trench; and determining an overlay parameter based on a difference between the trench center-of-gravity and the structure center-of-gravity.Type: GrantFiled: May 13, 2016Date of Patent: October 30, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Peter Moll, Martin Schmidt, Carsten Hartig, Matthias Ruhm, Stefan Thierbach, Stefan Rongen, Daniel Fischer, Andreas Schuring, Guido Überreiter
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Patent number: 10048311Abstract: A semiconductor test structure is provided for detecting raised source/drain regions-gate electrode shorts, including a semiconductor substrate, FETs formed on the semiconductor substrate, raised source/drain regions of the FETs formed on the semiconductor substrate, a gate electrode structure comprising multiple gate electrodes of the FETs arranged in parallel to each other, and a first electrical terminal electrically connected to the gate electrode structure, and wherein no electrical contacts to the raised source/drain regions are present between the multiple gate electrodes of the gate electrode structure.Type: GrantFiled: September 9, 2015Date of Patent: August 14, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Hans-Peter Moll, Uwe Dersch, Ricardo Pablo Mikalo
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Patent number: 9960184Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the semiconductor substrate, and a semiconductor layer positioned above the buried insulating layer. A shallow trench isolation (STI) structure is positioned in the SOI wafer and separates a first region of the SOI wafer from a second region of the SOI wafer, wherein the semiconductor layer is not present above the buried insulating layer in the first region, and wherein the buried insulating layer and the semiconductor layer are not present in at least a first portion of the second region adjacent to the STI structure. A dielectric layer is positioned above the buried insulating layer in the first region, and a conductive layer is positioned above the dielectric layer in the first region.Type: GrantFiled: July 10, 2017Date of Patent: May 1, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Jan Hoentschel, Peter Baars, Hans-Peter Moll
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Publication number: 20170330782Abstract: Methods for in-die overlay reticle measurement and the resulting devices are disclosed. Embodiments include providing parallel structures in a first layer on a substrate; determining measurement sites, in a second layer above the first layer, void of active integrated circuit elements; forming overlay trenches, in the measurement sites and parallel to the structures, exposing sections of the structures, wherein each overlay trench is aligned over a structure and over spaces between the structure and adjacent structures; determining a trench center-of-gravity of an overlay trench; determining a structure center-of-gravity of a structure exposed in the overlay trench; and determining an overlay parameter based on a difference between the trench center-of-gravity and the structure center-of-gravity.Type: ApplicationFiled: May 13, 2016Publication date: November 16, 2017Inventors: Peter MOLL, Martin SCHMIDT, Carsten HARTIG, Matthias RUHM, Stefan THIERBACH, Stefan RONGEN, Daniel FISCHER, Andreas SCHURING, Guido ÜBERREITER
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Publication number: 20170317108Abstract: A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the semiconductor substrate, and a semiconductor layer positioned above the buried insulating layer. A shallow trench isolation (STI) structure is positioned in the SOI wafer and separates a first region of the SOI wafer from a second region of the SOI wafer, wherein the semiconductor layer is not present above the buried insulating layer in the first region, and wherein the buried insulating layer and the semiconductor layer are not present in at least a first portion of the second region adjacent to the STI structure. A dielectric layer is positioned above the buried insulating layer in the first region, and a conductive layer is positioned above the dielectric layer in the first region.Type: ApplicationFiled: July 10, 2017Publication date: November 2, 2017Inventors: Jan Hoentschel, Peter Baars, Hans-Peter Moll
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Patent number: 9761689Abstract: The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a spacer removal after silicide formation is avoided and silicide overhang is suppressed. In some aspects of the present disclosure, a method of forming a semiconductor device is provided wherein a gate structure is provided over an active region of a semiconductor substrate, the gate structure including a gate electrode material and sidewall spacers. At least one of the gate electrode material and the sidewall spacers are shaped by applying a shaping process to the gate structure and a silicide portion is formed on the shaped gate structure.Type: GrantFiled: September 12, 2014Date of Patent: September 12, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Dominic Thurmer, Hans-Juergen Thees, Kai Frohberg, Peter Moll, Heike Scholz
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Patent number: 9735174Abstract: A method of manufacturing a semiconductor device including a capacitor structure is provided, including the steps of providing an SOI wafer comprising a substrate, a buried oxide (BOX) layer formed over the substrate and a semiconductor layer formed over the BOX layer, removing the semiconductor layer in a first region of the wafer to expose the BOX layer, forming a dielectric layer over the exposed BOX layer in the first region, and forming a conductive layer over the dielectric layer. Moreover, a semiconductor device including a capacitor formed on a wafer is provided, wherein the capacitor comprises a first capacitor electrode comprising a doped semiconductor substrate of the wafer, a capacitor insulator comprising an ultra-thin BOX layer of the wafer and a high-k dielectric layer formed on the ultra-thin BOX layer, and a second capacitor electrode comprising a conductive layer formed over the high-k dielectric layer.Type: GrantFiled: January 14, 2015Date of Patent: August 15, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Jan Hoentschel, Peter Baars, Hans-Peter Moll
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Publication number: 20170162557Abstract: A semiconductor device is provided including a fully depleted silicon-on-insulator (FDSOI) substrate and a charge pump device, wherein the FDSOI substrate comprises a semiconductor bulk substrate, and the charge pump device comprises a transistor device formed in and on the FDSOI substrate, and a trench capacitor formed in the semiconductor bulk substrate and electrically connected to the transistor device.Type: ApplicationFiled: December 3, 2015Publication date: June 8, 2017Inventors: Hans-Peter Moll, Peter Baars, Juergen Faul
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Patent number: 9673115Abstract: The present disclosure provides a test structure which includes an SOI substrate having an active semiconductor layer, a buried insulating material layer, and a base substrate, wherein the active semiconductor layer is formed on the buried insulating material layer, which, in turn, is formed on the base substrate. The test structure further includes a contact which is formed on the active semiconductor layer and electrically coupled to the active semiconductor layer. Herein, the contact has a tip portion extending through the active semiconductor layer into the buried insulating material layer.Type: GrantFiled: November 5, 2015Date of Patent: June 6, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Hans-Peter Moll, Dieter Lipp, Stefan Richter
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Publication number: 20170133287Abstract: The present disclosure provides a test structure which includes an SOI substrate having an active semiconductor layer, a buried insulating material layer, and a base substrate, wherein the active semiconductor layer is formed on the buried insulating material layer, which, in turn, is formed on the base substrate. The test structure further includes a contact which is formed on the active semiconductor layer and electrically coupled to the active semiconductor layer. Herein, the contact has a tip portion extending through the active semiconductor layer into the buried insulating material layer.Type: ApplicationFiled: November 5, 2015Publication date: May 11, 2017Inventors: Hans-Peter Moll, Dieter Lipp, Stefan Richter
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Patent number: 9627409Abstract: A semiconductor device with a metal-containing layer, a first semiconductor layer, that is formed on top of the metal-containing layer, and a resistor that is formed in the metal-containing layer and that is contacted through the first semiconductor layer is provided. Furthermore, a method of manufacturing a semiconductor device is provided, wherein the method comprises manufacturing of a resistor with the following steps: formation of a metal-containing layer over a wafer, particularly a SOI wafer, formation of a first semiconductor layer on top of the metal-containing layer and formation of a contact through the semiconductor layer to the metal-containing layer.Type: GrantFiled: December 29, 2015Date of Patent: April 18, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Hans-Peter Moll, Andrei Sidelnicov, Maciej Wiatr