Patents by Inventor Peter Moon

Peter Moon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8227335
    Abstract: Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper lines may also be covered with a noble metal.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: July 24, 2012
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Valery M. Dubin, Michael L. McSwiney, Peter Moon
  • Publication number: 20080044999
    Abstract: In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one air gap between the second at least one interconnect and the third layer, and at least one shunt selectively covering the first and second at least one interconnects. In another embodiment, a method comprises forming a first layer comprising an ILD and a first at least one interconnect, forming a second layer over the first layer, the second layer having a second at least one interconnect, depositing at least one shunt over the first and second at least one interconnects, forming a third layer over the second layer, and evaporating a portion of the second layer to create at least one air gap between the second at least one interconnect and the third layer.
    Type: Application
    Filed: August 15, 2007
    Publication date: February 21, 2008
    Inventors: Valery Dubin, Peter Moon
  • Publication number: 20070298608
    Abstract: Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper lines may also be covered with a noble metal.
    Type: Application
    Filed: August 31, 2007
    Publication date: December 27, 2007
    Inventors: Steven Johnston, Valery Dubin, Michael McSwiney, Peter Moon
  • Publication number: 20070284744
    Abstract: In one embodiment, an apparatus comprises a first layer having at least one interconnect formed in an interlayer dielectric (ILD), a second layer formed over the first layer having a second at least one interconnect, a third layer formed over the second layer, the third layer defining at least one air gap between the second at least one interconnect and the third layer, and at least one shunt selectively covering the first and second at least one interconnects. In another embodiment, a method comprises forming a first layer comprising an ILD and a first at least one interconnect, forming a second layer over the first layer, the second layer having a second at least one interconnect, depositing at least one shunt over the first and second at least one interconnects, forming a third layer over the second layer, and evaporating a portion of the second layer to create at least one air gap between the second at least one interconnect and the third layer.
    Type: Application
    Filed: August 15, 2007
    Publication date: December 13, 2007
    Inventors: Valery Dubin, Peter Moon
  • Patent number: 7279423
    Abstract: Noble metal may be used as a non-oxidizing diffusion barrier to prevent diffusion from copper lines. A diffusion barrier may be formed of a noble metal formed over an adhesion promoting layer or by a noble metal cap over an oxidizable diffusion barrier. The copper lines may also be covered with a noble metal.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: October 9, 2007
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Valery M. Dubin, Michael L. McSwiney, Peter Moon
  • Publication number: 20060273431
    Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.
    Type: Application
    Filed: June 3, 2005
    Publication date: December 7, 2006
    Inventors: Jun He, Kevin Fischer, Ying Zhou, Peter Moon
  • Publication number: 20060157764
    Abstract: Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.
    Type: Application
    Filed: March 9, 2006
    Publication date: July 20, 2006
    Inventors: Makarem Hussein, Ebrahim Andideh, Peter Moon, Daniel Diana
  • Publication number: 20060131750
    Abstract: The present invention includes a method of providing a substrate; sequentially forming a seed layer over the substrate and forming a protection layer over the seed layer; and sequentially removing the protection layer and forming a conductor over the seed layer. The present invention further includes a structure having a substrate, the substrate having a device; an insulator disposed over the substrate, the insulator having an opening, the opening disposed over the device; a barrier layer disposed over the opening; a seed layer disposed over the barrier layer; and a protection layer disposed over the seed layer.
    Type: Application
    Filed: January 19, 2006
    Publication date: June 22, 2006
    Inventors: Valery Dubin, Peter Moon
  • Publication number: 20060076678
    Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.
    Type: Application
    Filed: November 16, 2005
    Publication date: April 13, 2006
    Inventors: Sarah Kim, Bob Martell, David Ayers, R. List, Peter Moon, Steven Towle, Anna George
  • Patent number: 6977435
    Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: December 20, 2005
    Assignee: Intel Corporation
    Inventors: Sarah E. Kim, Bob Martell, Dave Ayers, R. Scott List, Peter Moon, Anna M. George, legal representative, Steven Towle, deceased
  • Publication number: 20050236714
    Abstract: An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to other processing treatments, the porogen is decomposed and removed from at least a portion of the porous matrix, leaving voids defined by the porous matrix in areas previously occupied by the porogen. The resultant structure has a desirably low k value as a result of the porosity and materials comprising the porous matrix and porogen. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.
    Type: Application
    Filed: June 28, 2005
    Publication date: October 27, 2005
    Inventors: Jihperng Leu, Grant Kloster, David Gracias, Lee Rockford, Peter Moon, Chris Barns
  • Publication number: 20050181593
    Abstract: An inter-layer dielectric structure and method of making such structure are disclosed. A composite dielectric layer, initially comprising a porous matrix and a porogen, is formed. Subsequent to other processing treatments, the porogen is decomposed and removed from at least a portion of the porous matrix, leaving voids defined by the porous matrix in areas previously occupied by the porogen. The resultant structure has a desirably low k value as a result of the porosity and materials comprising the porous matrix and porogen. The composite dielectric layer may be used in concert with other dielectric layers of varying porosity, dimensions, and material properties to provide varied mechanical and electrical performance profiles.
    Type: Application
    Filed: November 21, 2002
    Publication date: August 18, 2005
    Inventors: Jihperng Leu, Grant Kloster, David Gracias, Lee Rockford, Peter Moon, Chris Barns
  • Publication number: 20050146048
    Abstract: A method for making a semiconductor device is provided including providing a substrate, and forming a dielectric layer over the substrate. The method also includes defining a damascene interconnect structure in the dielectric layer and forming a barrier layer over the dielectric layer and within the damascene interconnect structure where the barrier layer is tapered within the damascene interconnect structure.
    Type: Application
    Filed: December 30, 2003
    Publication date: July 7, 2005
    Inventors: Valery Dubin, Peter Moon, Kevin O'Brien
  • Patent number: 6908829
    Abstract: A method of forming an air gap intermetal layer dielectric (ILD) to reduce capacitive coupling between electrical conductors in proximity. The method entails forming first and second electrical conductors over a substrate, wherein the electrical conductors are laterally spaced apart by a gap. Then, forming a gap bridging dielectric layer that extends over the first electrical conductor, the gap, and the second electrical conductor. In order to form a bridge from one electrical conductor to the other electrical conductor, the gap bridging dielectric materials should have poor gap filling characteristics. This can be attained by selecting and/or modifying a dielectric material to have a sufficiently high molecular weight and/or surface tension characteristic such that the material does not substantially sink into the gap. An example of such a material is a spin-on-polymer with a surfactant and/or other additives.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: June 21, 2005
    Assignee: Intel Corporation
    Inventors: Makarem A. Hussein, Peter Moon, Jim Powers, Kevin P. O'Brien
  • Publication number: 20050084985
    Abstract: Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.
    Type: Application
    Filed: October 17, 2003
    Publication date: April 21, 2005
    Inventors: Makarem Hussein, Ebrahim Andideh, Peter Moon, Daniel Diana
  • Publication number: 20050082584
    Abstract: Embodiments of the invention provide a method for producing ferroelectric polymer devices (FPMDs) employing conditions that avoid or reduce detrimental impact on the ferroelectric polymer film. For one embodiment, a damascene patterning metallization technique is used. For one embodiment a first metal layer is deposited on a substrate to form the bottom electrode for the FPMD. The first metal layer is capped with a selectively deposited diffusion barrier. A layer of ferroelectric polymer film is then deposited on the first conductive layer. The ferroelectric polymer film is planarized. A second metal layer is deposited on the ferroelectric polymer film layer to form the top electrode of the FPMD. The second metal layer is deposited such that the ferroelectric polymer film is not substantially degraded. For various alternative embodiments the various component processes may be accomplished at temperatures far below those employed in a conventional damascene patterning metallization process.
    Type: Application
    Filed: December 7, 2004
    Publication date: April 21, 2005
    Inventors: Makarem Hussein, Ebrahim Andideh, Peter Moon, Daniel Diana
  • Publication number: 20050051894
    Abstract: A process flow to make an interconnect structure with one or more thick metal layers under Controlled Collapse Chip Connection (C4) bumps at a die or wafer level. The interconnect structure may be used in a backend interconnect of a microprocessor. The one or more integrated thick metal layers may improve power delivery and reduce mechanical stress to a die at a die/package interface.
    Type: Application
    Filed: September 9, 2003
    Publication date: March 10, 2005
    Inventors: Sarah Kim, Bob Martell, David Ayers, R. List, Peter Moon, Steven Towle, Anna George
  • Publication number: 20050042874
    Abstract: A thermally decomposable sacrificial material is deposited in a void or opening in a dielectric layer on a semiconductor substrate. The thermally decomposable sacrificial material may be removed without damaging or removing the dielectric layer. The thermally decomposable sacrificial material may be a combination of organic and inorganic materials, such as a hydrocarbon-siloxane polymer hybrid.
    Type: Application
    Filed: September 29, 2004
    Publication date: February 24, 2005
    Inventors: Robert Meagley, Peter Moon, Kevin O'Brien
  • Patent number: D893200
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: August 18, 2020
    Assignee: Moonster Products Ltd
    Inventors: Peter Moon, Dharmendra Kumuwat
  • Patent number: D955475
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: June 21, 2022
    Assignee: Moonster Products LTD.
    Inventors: Peter Moon, Yunardi Bardo