Patents by Inventor Peter Moschak
Peter Moschak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120228014Abstract: A circuitized substrate for use in such electrical structures as information handling systems wherein the substrate includes a capacitive substrate as part thereof. The capacitive substrate includes a thin film layer of capacitive material strategically positioned on a conductive layer relative to added electrically conductive elements to in turn provide a plurality of internal capacitors within the final circuitized substrate during operation thereof. A method of making such a circuitized substrate is also provided.Type: ApplicationFiled: March 8, 2011Publication date: September 13, 2012Applicant: Endicott Interconnect Technologies, Inc.Inventors: Rabindra N. Das, Mark D. Poliks, Voya R. Markovich, Peter A. Moschak
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Publication number: 20110173809Abstract: Apparatus and method for making circuitized substrates using a continuous roll format in which a layer of conductor is fed into the apparatus, layers of photo-imageable dielectric are applied to opposite sides of the conductor layer, thru-holes are formed through the composite, and then metal layers are added over the dielectric and then patterns (e.g., circuit) are formed therein. Several operations are performed in addition to these to form the final end product, a circuitized substrate (e.g., printed circuit board), all while the conductor layer of the product is retained in a solid format, up to the final separation from the continuous layer.Type: ApplicationFiled: January 20, 2010Publication date: July 21, 2011Inventors: John M. Lauffer, Voya R. Markovich, James J. McNamara, JR., Peter A. Moschak
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Patent number: 7977034Abstract: Apparatus and method for making circuitized substrates using a continuous roll format in which a layer of conductor is fed into the apparatus, layers of photo-imageable dielectric are applied to opposite sides of the conductor layer, thru-holes are formed through the composite, and then metal layers are added over the dielectric and then patterns (e.g., circuit) are formed therein. Several operations are performed in addition to these to form the final end product, a circuitized substrate (e.g., printed circuit board), all while the conductor layer of the product is retained in a solid format, up to the final separation from the continuous layer.Type: GrantFiled: January 20, 2010Date of Patent: July 12, 2011Assignee: Endicott Interconnect Technologies, Inc.Inventors: John M. Lauffer, Voya R. Markovich, James J. McNamara, Jr., Peter A. Moschak
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Patent number: 7827682Abstract: Apparatus and method for making circuitized substrates using a continuous roll format in which a layer of conductor is fed into the apparatus, layers of photo-imageable dielectric are applied to opposite sides of the conductor layer, thru-holes are formed through the composite, and then metal layers are added over the dielectric and then patterns (e.g., circuit) are formed therein. Several operations are performed in addition to these to form the final end product, a circuitized substrate (e.g., printed circuit board), all while the conductor layer of the product is retained in a solid format, up to the final separation from the continuous layer.Type: GrantFiled: April 21, 2005Date of Patent: November 9, 2010Assignee: Endicott Interconnect Technologies, Inc.Inventors: John M. Lauffer, Voya R. Markovich, James J. McNamara, Jr., Peter A. Moschak
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Publication number: 20060240364Abstract: Apparatus and method for making circuitized substrates using a continuous roll format in which a layer of conductor is fed into the apparatus, layers of photo-imageable dielectric are applied to opposite sides of the conductor layer, thru-holes are formed through the composite, and then metal layers are added over the dielectric and then patterns (e.g., circuit) are formed therein. Several operations are performed in addition to these to form the final end product, a circuitized substrate (e.g., printed circuit board), all while the conductor layer of the product is retained in a solid format, up to the final separation from the continuous layer.Type: ApplicationFiled: April 21, 2005Publication date: October 26, 2006Applicant: Endicott Interconnect Technologies, Inc.Inventors: John Lauffer, Voya Markovich, James McNamara, Peter Moschak
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Patent number: 6830875Abstract: A method for forming an electronic structure. Provides is a layer that includes a cylindrical volume of a photoimageable dielectric (PID) material, an annular volume of the PID material circumscribing the cylindrical volume, and a remaining volume of the PID material circumscribing the annular volume. The layer is photolithograhically exposed to radiation. The annular volume is fully cured by the radiation. The remaining volume is partially cured by the remaining volume by said radiation. The method prevents curing of the cylindrical volume, wherein the PID material in the cylindrical volume remains uncured.Type: GrantFiled: October 7, 2002Date of Patent: December 14, 2004Assignee: International Business Machines CorporationInventors: Stephen J. Fuerniss, Gary Johansson, Ross W. Keesler, John M. Lauffer, Voya R. Markovich, Peter A. Moschak, David J. Russell, William E. Wilson
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Patent number: 6830627Abstract: The present invention is a persulfate microetchant composition especially useful for removing impurities from copper surfaces during fabrication of microelectronic packages. The microetchant formulation is characterized by its ability to selectively clean copper in the presence of nickel, nickel-phosphorous and noble metal alloys therefrom. Furthermore, no deleterious galvanic etching occurs in this microetchant-substrate system so that substantially no undercutting of the copper occurs. The combination of high selectivity and no undercutting allows for a simplification of the microelectronic fabrication process and significant improvements in the design features of the microelectronic package, in particular higher density circuits. The persulfate microetchant composition is stabilized with acid and phosphate salts to provide a process that is stable, fast acting, environmentally acceptable, has high capacity, and can be performed at room temperature.Type: GrantFiled: March 23, 1999Date of Patent: December 14, 2004Assignee: International Business Machines CorporationInventors: Kathleen L. Covert, John M. Lauffer, Peter A. Moschak
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Publication number: 20030047357Abstract: A through hole, and associated method of formation, through a layered structure that includes one or more layers having photoimageable dielectric (PID) material. The method forms a via within each such layer in isolation and then stacks the layers in a way that registers the vias over one another such that the through hole is formed as the sequentially registered vias. A sticker layer of the layered structure includes a cylindrical volume, an annular volume circumscribing the cylindrical volume, and a remaining volume surrounding the annular volume. The sticker layer preferentially includes a power plane of continuous metalization having a hole, wherein a perimeter of the hole surrounds the fully cured volume and circumscribes a portion of the remaining volume.Type: ApplicationFiled: October 7, 2002Publication date: March 13, 2003Inventors: Stephen J. Fuerniss, Joan Cangelosi, Gary Johansson, Ross W. Keesler, John M. Lauffer, Voya R. Markovich, Peter A. Moschak, David J. Russell, William E. Wilson
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Patent number: 6521328Abstract: The present invention is a persulfate etchant composition especially useful for dissolving copper during fabrication of microelectronic packages. The etchant is characterized by its ability to selectively etch copper in the presence of nickel, nickel-phosphorous and noble metal alloys therefrom. Furthermore, no deleterious galvanic etching occurs in this etchant-substrate system so that substantially no undercutting of the copper occurs. The combination of high selectivity and no undercutting allows for a simplification of the microelectronic fabrication process and significant improvements in the design features of the microelectronic package, in particular higher density circuits. The persulfate etchant composition is stabilized with acid and phosphate salts to provide a process that is stable, fast acting, environmentally acceptable, has high capacity, and can be performed at room temperature. A preferred etchant composition is 230 gm/liter sodium persulfate, 3 volume % phosphoric acid and 0.Type: GrantFiled: September 5, 2000Date of Patent: February 18, 2003Assignee: International Business Machines CorporationInventors: John M. Lauffer, Kathleen L. Covert, Peter A. Moschak
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Patent number: 6521844Abstract: An electronic structure. The electronic structure comprises a layer. The layer includes: a cylindrical volume; a fully cured annular volume of a photoimageable dielectric (PID) material circumscribing the cylindrical volume; and a partially cured remaining volume of the PID material circumscribing the annular volume. The cylindrical volume may include a via. The structure can include a power plane.Type: GrantFiled: October 29, 1999Date of Patent: February 18, 2003Assignee: International Business Machines CorporationInventors: Stephen J. Fuerniss, Gary Johansson, Ross W. Keesler, John M. Lauffer, Voya R. Markovich, Peter A. Moschak, David J. Russell, William E. Wilson
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Patent number: 6291776Abstract: A chip carrier constituted of an organic laminate which incorporates structure compensating for thermal deformation of the carrier. Moreover, disclosed is a method of counteracting the thermal deformations encountered by chip carriers, especially during solder reflow, which is predicated on the uniformly, equidistant positioning of metal-plated through-holes (PTH) formed in the chip carrier relative to contact pads. A plurality of plated through-holes (PTH) are positioned equidistantly relative to contact (BGA) pads on a surface of a substrate which is constituted of an organic laminate material, so as to be able to control both in-plane and out-of-plane thermal deformations in the chip carrier material which may be occasioned in a solder reflow furnace or oven.Type: GrantFiled: November 3, 1998Date of Patent: September 18, 2001Assignee: International Business Machines CorporationInventors: Voya R. Markovich, Peter A. Moschak, Seungbae Park, Sanjeev B. Sathe
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Patent number: 6156221Abstract: The present invention is a persulfate etchant composition especially useful for dissolving copper during fabrication of microelectronic packages. The etchant is characterized by its ability to selectively etch copper in the presence of nickel, nickel-phosphorous and noble metal alloys therefrom. Furthermore, no deleterious galvanic etching occurs in this etchant-substrate system so that substantially no undercutting of the copper occurs. The combination of high selectivity and no undercutting allows for a simplification of the microelectronic fabrication process and significant improvements in the design features of the microelectronic package, in particular higher density circuits. The persulfate etchant composition is stabilized with acid and phosphate salts to provide a process that is stable, fast acting, environmentally acceptable, has high capacity, and can be performed at room temperature. A preferred etchant composition is 230 gm/liter sodium persulfate, 3 volume % phosphoric acid and 0.Type: GrantFiled: October 2, 1998Date of Patent: December 5, 2000Assignee: International Business Machines CorporationInventors: John M. Lauffer, Kathleen L. Covert, deceased, Peter A. Moschak
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Patent number: 4786528Abstract: Reinforced synthetic polymer composite is treated by heating at a temperature and for a time sufficient to obtain a moisture content below that for the relative humidity level at which the composite is to be drilled and/or photoresist exposed; and then subjecting it to conditions to increase the moisture content to that for the relative humidity level of the drilling.Type: GrantFiled: May 20, 1986Date of Patent: November 22, 1988Assignee: International Business Machines CorporationInventors: William J. Amelio, Voya Markovich, William J. McCarthy, Allen F. Moring, Peter A. Moschak, Douglas H. Strope