Abstract: A compactor includes test data inputs that are connectable to circuit outputs of an electrical circuit, test comparison inputs, and test data outputs. The compactor further includes a number of H matrix XOR gates arranged as a switching mechanism between the test data inputs and the test data outputs such that data applied to the test data inputs is produced at the test data outputs compressed in accordance with coefficients of an H matrix of an error-correcting code, and compensation XOR gates arranged between the test data inputs and the test data outputs, each compensation XOR gate including an input for receiving a compensation value.

Abstract: A semiconductor device includes a radio frequency circuit and a programmable logic circuit electrically coupled to the radio frequency circuit.

Abstract: A compactor includes test data inputs that are connectable to circuit outputs of an electrical circuit, test comparison inputs, and test data outputs. The compactor further includes a number of H matrix XOR gates arranged as a switching mechanism between the test data inputs and the test data outputs such that data applied to the test data inputs is produced at the test data outputs compressed in accordance with coefficients of an H matrix of an error-correcting code, and compensation XOR gates arranged between the test data inputs and the test data outputs, each compensation XOR gate including an input for receiving a compensation value.

Abstract: A compactor includes test data inputs that are connectable to circuit outputs of an electrical circuit, test comparison inputs, and test data outputs. The compactor further includes a number of H matrix XOR gates arranged as a switching mechanism between the test data inputs and the test data outputs such that data applied to the test data inputs is produced at the test data outputs compressed in accordance with coefficients of an H matrix of an error-correcting code, and compensation XOR gates arranged between the test data inputs and the test data outputs, each compensation XOR gate including an input for receiving a compensation value.

Abstract: A compactor includes test data inputs that are connectable to circuit outputs of an electrical circuit, test comparison inputs, and test data outputs. The compactor further includes a number of H matrix XOR gates arranged as a switching mechanism between the test data inputs and the test data outputs such that data applied to the test data inputs is produced at the test data outputs compressed in accordance with coefficients of an H matrix of an error-correcting code, and compensation XOR gates arranged between the test data inputs and the test data outputs, each compensation XOR gate including an input for receiving a compensation value.

Abstract: An integrated circuit is characterized in that circuit parts contained therein are connected to one another via an interface containing at least one scan register chain. The at least one scan register chain is configured such that data can be input into the scan register chain either via the output terminals of one of the circuit parts or via the input and/or output terminals of the integrated circuit. In addition, data can be output from the scan register chain either at the input terminals of one of the circuit parts or at the input and/or output terminals of the integrated circuit.

Abstract: A semiconductor memory is subdivided into a plurality of function units and has m leads addressable from outside, internal signal lines leading from the function units to the leads, internal signal lines connecting the function units with one another, and a test unit recognizing a test mode from a code word applied to k leads, where k.ltoreq.m. A device switches over from a memory mode to the test mode. The test unit decouples at least one of the signal lines leading to the leads from an associated lead of the semiconductor memory and connects the lead to an internal signal line connecting the function units.

Abstract: An integrated semiconductor memory includes a parallel test device and block groups. The parallel test device is used for writing in and evaluating data to be written into and read out of the semiconductor memory. Several groups of memory cells can be simultaneously tested for operation in a test mode, with each group being disposed along a respective word line. The data read out during the process can be evaluated by the parallel test device. The result of the evaluation is present, separately for each group of memory cells, on I/O data lines of the semiconductor memory. The semiconductor memory can also have redundant memory cells, in which case defective memory cells or groups of memory cells can be replaced in connection with the test mode.