Abstract: Techniques are described for providing consistent memory operations and security across electronic circuitry components having disparate memory and/or security architectures when integrating such disparately architected components within a single system, such as a system on chip. A programmable logical hierarchy of isolated memory region (IMR) enforcement circuits is provided to protect such IMRs, allowing or preventing memory access requests from one of multiple distinct circuitry components based on configuration registers for the IMR enforcement circuits. Integration of multiple trust domain architectures associated with the multiple distinct circuitry components is facilitated via trust domain conversion bridge circuitry that includes translation logic for generating information in accordance with a first trust domain architecture based on information provided in accordance with a distinct second trust domain architecture.

Abstract: Techniques are described for providing consistent memory operations and security across electronic circuitry components having disparate memory and/or security architectures when integrating such disparately architected components within a single system, such as a system on chip. A programmable logical hierarchy of isolated memory region (IMR) enforcement circuits is provided to protect such IMRs, allowing or preventing memory access requests from one of multiple distinct circuitry components based on configuration registers for the IMR enforcement circuits. Integration of multiple trust domain architectures associated with the multiple distinct circuitry components is facilitated via trust domain conversion bridge circuitry that includes translation logic for generating information in accordance with a first trust domain architecture based on information provided in accordance with a distinct second trust domain architecture.

Abstract: Techniques are described for providing consistent memory operations and security across electronic circuitry components having disparate memory and/or security architectures when integrating such disparately architected components within a single system, such as a system on chip. A programmable logical hierarchy of isolated memory region (IMR) enforcement circuits is provided to protect such IMRs, allowing or preventing memory access requests from one of multiple distinct circuitry components based on configuration registers for the IMR enforcement circuits. Integration of multiple trust domain architectures associated with the multiple distinct circuitry components is facilitated via trust domain conversion bridge circuitry that includes translation logic for generating information in accordance with a first trust domain architecture based on information provided in accordance with a distinct second trust domain architecture.

Abstract: In one example, a system for managing access to hardware components includes a processor to manage a transition of a component from a known trusted first state and a context of a first application to a known trusted second state and a context of a second application based on trusted meta-data. The processor can also prevent contamination across the known trusted state of each application based on the trusted meta-data associated with each application. Additionally, the processor can detect a change of a trust boundary from the first application to the second application, save the first state of the first application accessing the component, remove said first state from the component, initialize and load the second state of the second application accessing the component, and execute the second application via the component based on the second state.

Abstract: Various embodiments for providing datapath security in a system-on-a-chip (SOC) device are described. In one embodiment, an apparatus may comprise a security controller to configure one or more functional units connected to a shared on-chip bus embedded in an SOC device to communicate with other functional units through one or more secure datapaths. The one or more functional units may be arranged to encrypt clear data, send encrypted data out through a secure datapath, receive encrypted data in from a secure datapath, and decrypt the encrypted data to recover clear data. Other embodiments are described and claimed.

Abstract: Methods and arrangements to extend message signal interrupt (MSI) transactions with additional data to reduce the latency associated with servicing interrupts included in the transactions are contemplated. Some embodiments may comprise a chipset that transmits the MSI to a processor to service the interrupt. The chipset may identify that a transaction is an extended MSI transaction by determining that the MSI has more than a four bytes. In several embodiments, the chipset may validate the MSI by determining that the MSI comprises at least six bytes and, in further embodiments, by determining that the extended MSI has a valid signature byte. Another embodiment comprises a processor to receive the extended MSI transaction and store the data to service the corresponding interrupt(s) in a low latency buffer. The processor may then service the interrupt(s) based upon the data when the processor becomes available.

Abstract: A video display controller may be implemented by a plurality of identical hardware blend stages that can be coupled together to produce the desired blend of video, graphics, overlays, and the like. Each of the various video planes to be blended can be multiplied by an alpha value to selectively apply alpha values to particular video planes. At least two video display windows may be selectively produced by the coupled blend stages.

Abstract: A method and apparatus to generate one or more graphics textures of a video image, wherein graphics textures have differing resolutions, and to render the video image as a graphics texture using the one or more graphics textures of differing resolutions. The one or more graphics textures have different resolutions, for example, a base resolution and one or more scaled resolutions. The graphics texture may be rendered and displayed on a surface of a multi-dimensional graphics object that may be manipulated on a display.

Abstract: An apparatus may include circuitry, a cryptographic module, and a key store. The circuitry may hold a private key associated with first media information. The cryptographic module may operate on the private key to generate a number of first control keys for decrypting the first media information. The key store may hold the number of first control keys from the cryptographic module. In some implementations, the key store may include sufficient storage to store more than one control key from each of a number of different crypto modules. In some implementations, the key store may receive multiple control keys simultaneously or nearly so. In some implementations, the key store may output multiple control keys simultaneously, or nearly so, for decrypting multiple streams of media information at the same time.

Abstract: Various embodiments for providing datapath security in a system-on-a-chip (SOC) device are described. In one embodiment, an apparatus may comprise a security controller to configure one or more functional units connected to a shared on-chip bus embedded in an SOC device to communicate with other functional units through one or more secure datapaths. The one or more functional units may be arranged to encrypt clear data, send encrypted data out through a secure datapath, receive encrypted data in from a secure datapath, and decrypt the encrypted data to recover clear data. Other embodiments are described and claimed.

Abstract: An apparatus may include circuitry to permanently and inaccessibly store a first private key that is a shared secret between a manufacturer of the circuitry and a first vendor of first encrypted media information. It may also include a key ladder to provide plural layers of encryption to the first private key to generate a first result for decrypting the first encrypted media information. A cryptographic module may encrypt the first private key to generate a second result for a security purpose other than decrypting media information. The module also may include a key ladder, and the apparatus may include other key ladders using the private key.

Abstract: A method and apparatus to generate one or more graphics textures of a video image, wherein graphics textures have differing resolutions, and to render the video image as a graphics texture using the one or more graphics textures of differing resolutions. The one or more graphics textures have different resolutions, for example, a base resolution and one or more scaled resolutions. The graphics texture may be rendered and displayed on a surface of a multi-dimensional graphics object that may be manipulated on a display.

Abstract: A discussion of a local memory with at least a command block section and a cache section that facilitates an efficient interrupt processing. The command-block section is allocated on a per interrupt basis and contains pointers to cache-lines. When an interrupt is recognized an interrupt, the proposal uses the pointers in the command-block to prefetch the corresponding cache-lines from the cache section of the local memory, which it loads into its local cache buffer. Thus, when the CPU recognizes an interrupt, the information for the context-switch is already available in cache.

Abstract: Methods and arrangements to extend message signal interrupt (MSI) transactions with additional data to reduce the latency associated with servicing interrupts included in the transactions are contemplated. Some embodiments may comprise a chipset that transmits the MSI to a processor to service the interrupt. The chipset may identify that a transaction is an extended MSI transaction by determining that the MSI has more than a four bytes. In several embodiments, the chipset may validate the MSI by determining that the MSI comprises at least six bytes and, in further embodiments, by determining that the extended MSI has a valid signature byte. Another embodiment comprises a processor to receive the extended MSI transaction and store the data to service the corresponding interrupt(s) in a low latency buffer. The processor may then service the interrupt(s) based upon the data when the processor becomes available.

Abstract: A system to monitor performance of a computing device includes a first bridge to interface with a first set of devices, and a second bridge to interface with a second set of devices. Configuration registers store configuration data associated with the second set of devices, and are accessible through the second bridge. A hub interface allows data to transfer downstream from the first bridge to the second bridge, and allows data to transfer upstream from the second bridge to the first bridge. A controller, external to the first and second bridges, accesses the configuration registers via the second bridge. A logic device allows the second bridge to send data to, and receive data from, the controller.

Abstract: A method and apparatus to manage power consumption of a system is provided. The method may include altering power consumption of a stream processing system based on information from a data stream to be processed by the stream processing system. Other embodiments are described and claimed.

Abstract: A variable speed bus has its frequency adjusted based upon bandwidth requirements of active units coupled to a variable speed bus. As units coupled to the bus are stopped, bandwidth requirements are lowered and the bus frequency is reduced in response to the lowered bandwidth requirements. An arbiter selects an appropriate arbitration configuration based on which units are active and which are stopped. The arbitration configuration is adjusted to ensure that the bandwidth requirements of the active units are sustained despite the reduced clock frequency.

Abstract: An embodiment involves throttling a bus frequency based upon incoming arbitration requests from units or devices coupled to a bus. Arbitration circuitry monitors request rates from each requestor and increases or decreases the bus frequency in order to meet the bandwidth levels requested. When the bandwidth requirements increase, the bus frequency increases. When the bandwidth requirements are reduced, the bus frequency is reduced to reduce power consumption. No software intervention is required to adjust the bus bandwidth.

Abstract: According to one embodiment a computer system is disclosed. The computer system includes a central processing unit (CPU) and a memory device, coupled to the CPU. The memory device includes a charge pump circuit to amplify a first voltage, and a voltage detection circuit coupled to the charge pump circuit to disable the charge pump circuit if a second voltage is detected.

Abstract: Machine-readable media, methods, and apparatus are described to maintain synchronization of redundant devices. In one embodiment, a transmitter sends data packets to a receiver via a primary channel. Further, the transmitter may throttle data packet transfers on the primary channel based upon credit limits associated with the primary channel and redundancy channels that couple the transmitter to redundant receivers.