Abstract: In a successive-approximation analog-to-digital conversion application, charge injection offset at the sample input of the comparator resulting from the changing DAC reference voltage, is converted to a fixed, systematic offset. In the comparator differential input stage, the reference or driven input device is turned off during a sample time, prior to beginning the conversion process, so that substantially all of a predetermined bias current flows in the sample side of the comparator. Given this initial condition, the change in input voltage through conversion is a fixed function of the device geometry, bias current and gain, independent of the sample voltage, and therefore may be calibrated out of the system. The comparator input stage includes a differential pair of MOS transistors. A CMOS transmission gate is coupled between the DAC output and the reference comparator input. A switch transistor is coupled between the reference input, i.e. the gate of M2, and Vdd for biasing off M2 during sample time.

Abstract: A latching CMOS comparator method and circuit are disclosed. The comparator circuit includes a differential input stage and a latching stage. The input stage includes a differential amplifier (MP3,MP4) and a Moore Mirror load. The load includes a first cross-coupled amplifier pair (MN3,MN4), and a pair of diode-connected transistors (MN1,MN2) coupled in parallel to the first amplifier to control gain. The input stage devices are sized to provide a gain on the order of 10 to 20. The latch clock signal (CLK) is isolated from the input stage to avoid injected charge offset error. The second or latching stage includes a second cross-coupled transistor amplifier (MP7,MP8) coupled to the input stage to provide additional gain. The latch clock signal is provided to a digital switch (MP9,MP10) which controls gain in the second amplifier.