Abstract: Several I/O channel processes time share a data pipeline processor. For each stage of the pipeline, there is a control memory and means for shifting an address from memory to memory as a process in the pipeline proceeds from stage to stage. The number of processes is greater than the number of pipeline stages, and storage is provided for the data and for the addresses while a process is out of the pipeline, waiting to be re-entered for a next pass. A storage array for holding the addresses is arranged to hold addresses for four activity levels for each process. While an address is held in the array it can be modified for the next pass through the pipeline or the process can be switched from a lower priority level activity to a higher level activity.