Patents by Inventor Peter N. Wood

Peter N. Wood has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7321210
    Abstract: Disclosed is a variable speed brushless direct current (BLDC) motor drive circuit. The circuit includes a plurality of high-side and low-side controlled switches coupled in a three-phase bridge configuration for commutating a BLDC motor, each phase of the bridge being connected to a corresponding phase of the motor, a controller for providing a drive signal to drive each of the high-side and low-side switches, and a speed control loop for controlling the motor by PWM of a DC bus voltage to achieve a constant motor speed.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: January 22, 2008
    Assignee: International Rectifier Corporation
    Inventor: Peter N Wood
  • Patent number: 7102625
    Abstract: A cradle is arranged to be clipped onto or otherwise removably secured to a writing instrument, and to hold a camera or other optical image capture device so that images of marks made by the writing instrument may be captured and transmitted to a processor for remote display, storage, and/or processing.
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: September 5, 2006
    Inventor: Peter N. Woods
  • Publication number: 20030214489
    Abstract: A cradle is arranged to be clipped onto or otherwise removably secured to a writing instrument, and to hold a camera or other optical image capture device so that images of marks made by the writing instrument may be captured and transmitted to a processor for remote display, storage, and/or processing.
    Type: Application
    Filed: May 14, 2002
    Publication date: November 20, 2003
    Inventor: Peter N. Woods
  • Patent number: 6002213
    Abstract: A MOS gate drive (MGD) integrated circuit drives a pair of MOS gated power semiconductor devices such as are used in a half bridge circuit to drive a load in a resonant power supply circuit or to drive a gas discharge lamp in a ballast circuit. The gate drive circuit includes dead time circuitry which prevents simultaneous conduction in both MOS gated devices. The duration of the dead time is controlled in response to a feedback signal that is sensed from the output supplied to the load or the lamp. A dimming function is attained by controlling the voltage of the feedback signal.
    Type: Grant
    Filed: September 13, 1996
    Date of Patent: December 14, 1999
    Assignee: International Rectifier Corporation
    Inventor: Peter N. Wood
  • Patent number: 5932974
    Abstract: A lamp ballast circuit drives at least one gas discharge illumination device and includes first and second MOS-gated power semiconductor devices connected in a half-bridge configuration and coupled across a d-c supply with a common terminal located at the node between the devices for supplying an output signal to the illumination device. A self-oscillating driver circuit includes respective outputs for driving the power semiconductor devices and has at least one operating voltage supply terminal. When the illumination device fails or is removed, a protection circuit, electrically coupled to the illumination device, removes the operating voltage supplied to the supply terminal. The protection circuit includes a transformer/inductor coupled to the illumination device or a switch that is responsive to the voltage across the illumination device. Additionally, a soft-starting circuit can be provided for gradually increasing the voltage across the illumination device prior to igniting the illumination device.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: August 3, 1999
    Assignee: International Rectifier Corporation
    Inventor: Peter N. Wood
  • Patent number: 5805433
    Abstract: A power supply includes a half bridge transistor circuit coupled across a DC bus, where the half bridge transistor circuit includes a high-side transistor and a low-side transistor and produces an output pulse width modulation (PWM) signal and a self oscillating half bridge driver circuit for producing first and second control PWM signals in response to an external threshold signal. The first control PWM signal is coupled to a control terminal of the high-side transistor and the second control PWM signal is coupled to a control terminal of the low-side transistor. The power supply also includes a low pass filter for receiving the output PWM signal and producing a DC output voltage therefrom across a pair of output terminals and a programmable voltage regulating device having an input terminal coupled to the DC output voltage and an output terminal coupled to the external threshold voltage.
    Type: Grant
    Filed: April 16, 1997
    Date of Patent: September 8, 1998
    Assignee: International Rectifier Corporation
    Inventor: Peter N. Wood
  • Patent number: 5796215
    Abstract: A half bridge driver chip for driving a resonant load, such as a ballast, has first and second pairs to which an oscillation frequency timing circuit, matched to the resonant frequency of the load. A constant voltage drop circuit is connected to these input pins to vary the voltage at the pins as a linear function of the input voltage V.sub.cc. Consequently, when V.sub.cc is increasing during the start-up of the circuit, the resonant frequency is initially high but decreases to its operation value as V.sub.cc increases. This produces a soft start characteristic and a timed preheat cycle of the resonant load. In one embodiment, the constant voltage drop circuit is a zener diode; in another embodiment, it is strings of anti-parallel connected diodes.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: August 18, 1998
    Assignee: International Rectifier Corporation
    Inventors: John Edward Parry, Peter N. Wood
  • Patent number: 5757141
    Abstract: A monolithic MOS gate driver chip is described for driving high side and low side power MOSFETs in a gas discharge lamp ballast circuit. The chip includes a timer circuit for generating a square output at the natural frequency of resonance of the lamp ballast. Dead time circuits are provided in the chip to prevent the simultaneous conduction of both high side and low side MOSFETs. The chip may be housed in a right pin DIP package.
    Type: Grant
    Filed: August 9, 1996
    Date of Patent: May 26, 1998
    Assignee: International Rectifier Corporation
    Inventor: Peter N. Wood
  • Patent number: 5747943
    Abstract: A monolithic MOS gate driver chip is described for driving high side and low side power MOSFETs in a gas discharge lamp ballast circuit. The chip includes a timer circuit for generating a square output at the natural frequency of resonance of the lamp ballast. Dead time circuits are provided in the chip to prevent the simultaneous conduction of both high side and low side MOSFETs. The chip may be housed in an eight pin DIP package.
    Type: Grant
    Filed: August 26, 1996
    Date of Patent: May 5, 1998
    Assignee: International Rectifier Corporation
    Inventors: Talbott M. Houk, Peter N. Wood
  • Patent number: 5559394
    Abstract: A monolithic MOS gate driver chip is described for driving high side and low side power MOSFETs in a gas discharge lamp ballast circuit. The chip includes a timer circuit for generating a square output at the natural frequency of resonance of the lamp ballast. Dead time circuits are provided in the chip to prevent the simultaneous conduction of both high side and low side MOSFETs. The chip may be housed in a right pin DIP package.
    Type: Grant
    Filed: August 11, 1995
    Date of Patent: September 24, 1996
    Assignee: International Rectifier Corporation
    Inventor: Peter N. Wood
  • Patent number: 5545955
    Abstract: A monolithic MOS gate driver chip is described for driving high side and low side power MOSFETs in a gas discharge lamp ballast circuit. The chip includes a timer circuit for generating a square output at the natural frequency of resonance of the lamp ballast. Dead time circuits are provided in the chip to prevent the simultaneous conduction of both high side and low side MOSFETs. The chip may be housed in a right pin DIP package.
    Type: Grant
    Filed: March 4, 1994
    Date of Patent: August 13, 1996
    Assignee: International Rectifier Corporation
    Inventor: Peter N. Wood
  • Patent number: 5387847
    Abstract: A ballast for a gas discharge lamp circuit has a d-c output which contains three series-connected diodes connected across the output terminals, a pair of capacitors connected from different respective nodes of the diodes to respective ones of the output terminals, and a resistor connected between two of the diodes. The resistor increases the circuit power factor to greater than 0.95.
    Type: Grant
    Filed: March 4, 1994
    Date of Patent: February 7, 1995
    Assignee: International Rectifier Corporation
    Inventor: Peter N. Wood
  • Patent number: 4511815
    Abstract: A high power MOSFET switching circuit which has a larger duty cycle is driven from the output winding of a saturable isolation transformer. The output winding is coupled to the gate of the MOSFET power switch through a series connected control MOSFET device having an inherent parallel-connected diode. The gate capacitance is charged through the diode and is discharged through the control MOSFET when it is turned on. The drive circuit is a low impedance circuit with full isolation between input and output terminals.
    Type: Grant
    Filed: August 15, 1983
    Date of Patent: April 16, 1985
    Assignee: International Rectifier Corporation
    Inventor: Peter N. Wood