Patents by Inventor Peter Ngee Ching Lim

Peter Ngee Ching Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7675339
    Abstract: A system and method for generating a delayed clock signal of an input clock signal involves selectively delaying the input clock signal to produce the delayed clock signal based on the duty cycle of the input clock signal and the duty cycle of a logic signal derived from a logic operation of the input clock signal and the delayed clock signal.
    Type: Grant
    Filed: February 9, 2007
    Date of Patent: March 9, 2010
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Peter Ngee Ching Lim, Cheng Huat Tan, Kin Soon Liew
  • Patent number: 7573603
    Abstract: A method and apparatus for processing image data are disclosed. The method includes the step of partitioning the image data into a plurality of data portions (?Page) for processing. Each data portion comprises a plurality of rows of pixels corresponding to at least one print swath height. The data portions are processed in a plurality of intermediate processing stages. The data portions are processed sequentially. The number of pixels per row of a data portion is determined to be just large enough ensure adequate output printing data for a given print head at all times. The processed data is then delivered to the print head in a just-in-time manner (JIT). An apparatus for processing the image data comprises an Application Specific Integrated Circuit (ASIC).
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: August 11, 2009
    Assignee: Avago Technologies Fiber IP (Singapore) Pte. Ltd.
    Inventors: Purushothaman Pattusamy, Peter Ngee Ching Lim
  • Publication number: 20080191764
    Abstract: A system and method for generating a delayed clock signal of an input clock signal involves selectively delaying the input clock signal to produce the delayed clock signal based on the duty cycle of the input clock signal and the duty cycle of a logic signal derived from a logic operation of the input clock signal and the delayed clock signal.
    Type: Application
    Filed: February 9, 2007
    Publication date: August 14, 2008
    Inventors: Peter Ngee Ching Lim, Chang Huat Tan, Kin Soon Liew
  • Publication number: 20040070791
    Abstract: A method and apparatus for processing image data are disclosed. The method includes the step of partitioning the image data into a plurality of data portions (&mgr;page) for processing. Each data portion comprises a plurality of rows of pixels corresponding to at least one print swath height. The data portions are processed in a plurality of intermediate processing stages. The data portions are processed sequentially. The number of pixels per row of a data portion is determined to be just large enough ensure adequate output printing data for a given print head at all times. The processed data is then delivered to the print head in a just-in-time manner (JIT). An apparatus for processing the image data comprises an Application Specific Integrated Circuit (ASIC).
    Type: Application
    Filed: October 9, 2003
    Publication date: April 15, 2004
    Inventors: Purushothaman Pattusamy, Peter Ngee Ching Lim