Patents by Inventor Peter Nicholas Manos
Peter Nicholas Manos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8896070Abstract: The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.Type: GrantFiled: April 13, 2012Date of Patent: November 25, 2014Assignee: Seagate Technology LLCInventors: Hyung-Kyu Lee, YoungPil Kim, Peter Nicholas Manos, Maroun Khoury, Dadi Setiadi, Chulmin Jung, Hsing-Kuen Liou, Paramasiyan Kamatchi Subramanian, Yongchul Ahn, Jinyoung Kim, Antoine Khoueir
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Publication number: 20140097400Abstract: A vertical transistor includes a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening ion species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.Type: ApplicationFiled: December 10, 2013Publication date: April 10, 2014Applicant: SEAGATE TECHNOLOGY LLCInventors: Young Pil Kim, Hyung-Kew Lee, Peter Nicholas Manos, Chulmin Jung, Maroun Georges Khoury, Dadi Setiadi
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Patent number: 8617952Abstract: A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.Type: GrantFiled: September 28, 2010Date of Patent: December 31, 2013Assignee: Seagate Technology LLCInventors: Young Pil Kim, Hyung-Kew Lee, Peter Nicholas Manos, Chulmin Jung, Maroun Georges Khoury, Dadi Setiadi
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Publication number: 20130302948Abstract: A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell.Type: ApplicationFiled: July 22, 2013Publication date: November 14, 2013Applicant: SEAGATE TECHNOLOGY LLCInventors: Dadi Setiadi, Peter Nicholas Manos, Hsing-Kuen Liou, Paramasivan Kamatchi Subramanian, Young Pil Kim, Hyung-Kyu Lee, Maroun Georges Khoury, Chulmin Jung
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Publication number: 20120199915Abstract: The present invention is generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.Type: ApplicationFiled: April 13, 2012Publication date: August 9, 2012Applicant: Seagate Technology LLCInventors: Hyung-Kyu Lee, YoungPil Kim, Peter Nicholas Manos, Maroun Khoury, Dadi Setiadi, Chulmin Jung, Hsing-Kuen Liou, Paramasiyan Kamatchi Subramanian, Yongchul Ahn, Jinyoung Kim, Antoine Khoueir
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Patent number: 8208285Abstract: A semiconductor device for accessing non-volatile memory cell is provided. In some embodiments, the semiconductor device has a vertical stack of semiconductor layers including a source, a drain, and a well. An application of a drain-source bias voltage to the semiconductor device generates a punchthrough mechanism across the well to initiate a flow of current between the source and the drain.Type: GrantFiled: July 13, 2009Date of Patent: June 26, 2012Assignee: Seagate Technology LLCInventors: Maroun Georges Khoury, Hyung-Kyu Lee, Peter Nicholas Manos, Chulmin Jung, YoungPil Kim
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Patent number: 8193089Abstract: Various embodiments of the present invention are generally directed to a method of forming a conductive via plug in a semiconductor device. A first and second metal layer are electrically connected by a via plug that is formed by depositing a tungsten seed layer on a plurality of metal barrier layers within a recess using atomic layer deposition. The recess is then filled with tungsten using chemical vapor deposition.Type: GrantFiled: July 13, 2009Date of Patent: June 5, 2012Assignee: Seagate Technology LLCInventors: Antoine Khoueir, Yongchul Ahn, Peter Nicholas Manos, Shuiyan Huang, Ivan Petrov Ivanov
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Patent number: 8183126Abstract: Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.Type: GrantFiled: July 13, 2009Date of Patent: May 22, 2012Assignee: Seagate Technology LLCInventors: Hyung-Kyu Lee, YoungPil Kim, Peter Nicholas Manos, Maroun Khoury, Dadi Setiadi, Chulmin Jung, Hsing-Kuen Liou, Paramasiyan Kamatchi Subramanian, Yongchul Ahn, Jinyoung Kim, Antoine Khoueir
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Publication number: 20120080725Abstract: A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. An electrically conducting interconnect element is deposited onto at least selected vertical pillar transistors and a non-volatile variable resistive memory cell is deposited onto the electrically conducting interconnect layer to form a vertical transistor memory array.Type: ApplicationFiled: September 30, 2010Publication date: April 5, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Peter Nicholas Manos, Young Pil Kim, Hyung-Kyu Lee, Yongchul Ahn, Jinyoung Kim, Antoine Khoueir, Brian Lee, Dadi Setiadi
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Publication number: 20120074488Abstract: A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is implanted into the vertical pillar transistor top surface. Then the vertical pillar transistor side surface is oxidized to form a side surface oxide layer. The side surface oxide layer is removed to form vertical pillar transistor having rounded side surfaces.Type: ApplicationFiled: September 28, 2010Publication date: March 29, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Young Pil Kim, Hyung-Kyu Lee, Peter Nicholas Manos, Chulmin Jung, Maroun Georges Khoury, Dadi Setiadi
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Publication number: 20120074466Abstract: A memory array includes a base circuitry layer and a plurality of memory array layers stacked sequentially to form the memory array. Each memory array layer is electrically coupled to the base circuitry layer. Each memory array layer includes a plurality of memory units. Each memory unit includes a vertical pillar transistor electrically coupled to a memory cell.Type: ApplicationFiled: September 28, 2010Publication date: March 29, 2012Applicant: SEAGATE TECHNOLOGY LLCInventors: Dadi Setiadi, Peter Nicholas Manos, Hsing-Kuen Liou, Paramasivan Kamatchi Subramanian, Young Pil Kim, Hyung-Kyu Lee, Maroun Georges Khoury, Chulmin Jung
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Publication number: 20110170335Abstract: A semiconductor device for accessing non-volatile memory cell is provided. In some embodiments, the semiconductor device has a vertical stack of semiconductor layers including a source, a drain, and a well. An application of a drain-source bias voltage to the semiconductor device generates a punchthrough mechanism across the well to initiate a flow of current between the source and the drain.Type: ApplicationFiled: March 25, 2011Publication date: July 14, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Maroun Georges Khoury, Hyung-Kyu Lee, Peter Nicholas Manos, Chulmin Jung, YoungPil Kim
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Patent number: 7965538Abstract: Apparatus and method for providing overcurrent protection to a resistive random access memory (RRAM) cell during an RRAM formation process used to prepare the cell for normal read and write operations. In accordance with various embodiments, the RRAM cell is connected between a first control line and a second control line, and an active protection device (APD) is connected between the second control line and an electrical ground terminal. A formation current is applied through the RRAM cell, and an activation voltage is concurrently applied to the APD to maintain a maximum magnitude of the formation current below a predetermined threshold level.Type: GrantFiled: July 13, 2009Date of Patent: June 21, 2011Assignee: Seagate Technology LLCInventors: Yongchul Ahn, Antoine Khoueir, Shuiyuan Huang, Peter Nicholas Manos, Maroun Khoury
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Publication number: 20110006377Abstract: Various embodiments of the present invention are generally directed to an apparatus with embedded (bottom side) control lines for vertically stacked semiconductor elements, and a method for forming the same. In accordance with various embodiments, a first semiconductor wafer is provided with a first facing surface on which a first conductive layer is formed. The first semiconductor wafer is attached to a second semiconductor wafer to form a multi-wafer structure, the second semiconductor wafer having a second facing surface on which a second conductive wafer is formed. The first conductive layer is contactingly bonded to the second conductive layer to form an embedded combined conductive layer within said structure. Portions of the combined conductive layer are removed to form a plurality of spaced apart control lines that extend in a selected length or width dimension through said structure.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Hyung-Kyu Lee, YoungPil Kim, Peter Nicholas Manos, Maroun Khoury, Dadi Setiadi, Chulmin Jung, Hsing-Kuen Liou, Paramasiyan Kamatchi Subramanian, Yongchul Ahn, Jinyoung Kim, Antoine Khoueir
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Publication number: 20110007547Abstract: A semiconductor device for accessing non-volatile memory cell is provided. In some embodiments, the semiconductor device has a vertical stack of semiconductor layers including a source, a drain, and a well. An application of a drain-source bias voltage to the semiconductor device generates a punchthrough mechanism across the well to initiate a flow of current between the source and the drain.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Maroun Georges Khoury, Hyung-Kyu Lee, Peter Nicholas Manos, Chulmin Jung, YoungPil Kim
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Publication number: 20110006436Abstract: Various embodiments of the present invention are generally directed to a method of forming a conductive via plug in a semiconductor device. A first and second metal layer are electrically connected by a via plug that is formed by depositing a tungsten seed layer on a plurality of metal barrier layers within a recess using atomic layer deposition. The recess is then filled with tungsten using chemical vapor deposition.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Antoine Khoueir, Yongchul Ahn, Peter Nicholas Manos, Shuiyuan Huang, Ivan Petrov Ivanov
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Publication number: 20110007552Abstract: Apparatus and method for providing overcurrent protection to a resistive random access memory (RRAM) cell during an RRAM formation process used to prepare the cell for normal read and write operations. In accordance with various embodiments, the RRAM cell is connected between a first control line and a second control line, and an active protection device (APD) is connected between the second control line and an electrical ground terminal.Type: ApplicationFiled: July 13, 2009Publication date: January 13, 2011Applicant: SEAGATE TECHNOLOGY LLCInventors: Yongchul Ahn, Antoine Khoueir, Shuiyuan Huang, Peter Nicholas Manos, Maroun Khoury