Abstract: A memory is provided with a read data latch that latches a read data signal during a read operation to the memory responsive to a first binary value of a bypass signal. During a design-for-test bypass mode for the memory, a write data latch latches a data in signal from a scan chain to provide a write data signal. The read data latch responds to a second binary value of the bypass signal by latching the write data signal.

Abstract: Aspects of the disclosure are directed to a dynamic master slave flip flop circuit. In accordance with one aspect, the disclosure includes a master latch section configured to receive an input signal asserted at a HIGH state of the input signal; a clock circuit coupled to the master latch section, the clock circuit configured to execute a positive clock transition of a clock signal; and a slave latch section coupled to the master latch section and the clock circuit, the slave latch section configured to transition a state (Q) signal from a LOW state to a HIGH state of the state (Q) signal subsequent to the positive clock transition.

Abstract: An apparatus, including: a level shifter configured to: receive an input data signal in a first voltage domain; receive a reset signal in a second voltage domain; and generate an intermediate signal in the second voltage domain based on the input data signal and the reset signal; and a resettable latch configured to generate an output signal in the second voltage domain at an output in response to receiving the input data signal, the intermediate signal, the reset signal, and a clock signal in the second voltage domain, the output signal being based on logic states of the input data signal, the intermediate signal, the reset signal, and the clock signal, respectively.

Abstract: An apparatus, including: a level shifter configured to: receive an input data signal in a first voltage domain; receive a reset signal in a second voltage domain; and generate an intermediate signal in the second voltage domain based on the input data signal and the reset signal; and a resettable latch configured to generate an output signal in the second voltage domain at an output in response to receiving the input data signal, the intermediate signal, the reset signal, and a clock signal in the second voltage domain, the output signal being based on logic states of the input data signal, the intermediate signal, the reset signal, and the clock signal, respectively.

Abstract: A power-supply circuit for a memory includes a bitcell power-supply circuit and a bitcell power-control circuit. The bitcell power-supply circuit includes a first terminal coupled to a bitcell of the memory. The bitcell power-control circuit is coupled to the bitcell power-supply circuit, and controls the bitcell power-supply circuit in a write-assist mode to output a first voltage on the first terminal that is based on a ratio of capacitance of the bitcell and of capacitance of a charge-sharing capacitance. The bitcell power-control circuit further controls the bitcell power-supply circuit in a data-retention mode to output a second voltage on the first terminal that is about one diode drop below a voltage of a main power supply to the bitcell. The bitcell power-control circuit also controls the bitcell power-supply circuit in a power-down mode to turn off power output from the first terminal.

Abstract: A power-supply circuit for a memory includes a bitcell power-supply circuit and a bitcell power-control circuit. The bitcell power-supply circuit includes a first terminal coupled to a bitcell of the memory. The bitcell power-control circuit is coupled to the bitcell power-supply circuit, and controls the bitcell power-supply circuit in a write-assist mode to output a first voltage on the first terminal that is based on a ratio of capacitance of the bitcell and of capacitance of a charge-sharing capacitance. The bitcell power-control circuit further controls the bitcell power-supply circuit in a data-retention mode to output a second voltage on the first terminal that is about one diode drop below a voltage of a main power supply to the bitcell. The bitcell power-control circuit also controls the bitcell power-supply circuit in a power-down mode to turn off power output from the first terminal.

Abstract: Precharge circuitry for reading a data bit from a memory having at least two local bit lines comprises at least two precharge transistors for precharging the at least two local bit lines, at least two “keeper” transistors for keeping the at least two local bit lines, and a NAND gate for receiving the data bit from the memory via one of the at least two local bit lines and switching the at least two “keeper” transistors. The precharge circuitry does not need an additional inverter for switching any of the “keeper” transistors, thereby eliminating additional capacitance associated with the inverter and reducing unnecessary power consumption associated with the “keeper” transistors. Preferably, the transistors used in the precharge circuitry are p-channel metal-oxide-semiconductor field effect transistors (MOSFETs).