Abstract: Various embodiments herein relate to methods and systems for backscatter communication using pre-defined templates. In accordance with at least one embodiment, there is provided a backscattering communication system, comprising a transmitting unit, a backscattering tag, and a receiving unit. The transmitting unit is configured to transmit a signal comprising a transmitted frame including a pre-defined data payload. The backscattering tag is configured to: receive, from the transmitting unit, the signal comprising the transmitted frame; encode tag data over the pre-defined data payload to generate a modified data payload; and transmit a backscattered signal comprising a backscattered frame including the modified data payload.

Abstract: Various embodiments herein relate to methods and systems for backscatter communication using pre-defined templates. In accordance with at least one embodiment, there is provided a backscattering communication system, comprising a transmitting unit, a backscattering tag, and a receiving unit. The transmitting unit is configured to transmit a signal comprising a transmitted frame including a pre-defined data payload. The backscattering tag is configured to: receive, from the transmitting unit, the signal comprising the transmitted frame; encode tag data over the pre-defined data payload to generate a modified data payload; and transmit a backscattered signal comprising a backscattered frame including the modified data payload.

Abstract: In one embodiment an apparatus includes: a mixer to downconvert a radio frequency (RF) spectrum including at least a first RF signal of a first channel of interest and a second RF signal of a second channel of interest to at least a first second frequency signal and a second second frequency signal; a first digitizer to digitize the first second frequency signal to a first digitized signal, the first digitizer configured to operate as a low-pass analog-to-digital converter (ADC); a second digitizer to digitize the second second frequency signal to a second digitized signal, the second digitizer configured to operate as a band-pass ADC; and a digital processor to digitally process the first digitized signal and the second digitized signal.

Abstract: In one embodiment an apparatus includes: a mixer to downconvert a radio frequency (RF) spectrum including at least a first RF signal of a first channel of interest and a second RF signal of a second channel of interest to at least a first second frequency signal and a second second frequency signal; a first digitizer to digitize the first second frequency signal to a first digitized signal, the first digitizer configured to operate as a low-pass analog-to-digital converter (ADC); a second digitizer to digitize the second second frequency signal to a second digitized signal, the second digitizer configured to operate as a band-pass ADC; and a digital processor to digitally process the first digitized signal and the second digitized signal.

Abstract: In one embodiment an apparatus includes: a mixer to downconvert a radio frequency (RF) spectrum including at least a first RF signal of a first channel of interest and a second RF signal of a second channel of interest to at least a first second frequency signal and a second second frequency signal; a first digitizer to digitize the first second frequency signal to a first digitized signal, the first digitizer configured to operate as a low-pass analog-to-digital converter (ADC); a second digitizer to digitize the second second frequency signal to a second digitized signal, the second digitizer configured to operate as a band-pass ADC; and a digital processor to digitally process the first digitized signal and the second digitized signal.

Abstract: In one embodiment an apparatus includes: a mixer to downconvert a radio frequency (RF) spectrum including at least a first RF signal of a first channel of interest and a second RF signal of a second channel of interest to at least a first second frequency signal and a second second frequency signal; a first digitizer to digitize the first second frequency signal to a first digitized signal, the first digitizer configured to operate as a low-pass analog-to-digital converter (ADC); a second digitizer to digitize the second second frequency signal to a second digitized signal, the second digitizer configured to operate as a band-pass ADC; and a digital processor to digitally process the first digitized signal and the second digitized signal.

Abstract: In one embodiment an apparatus includes: a mixer to downconvert a radio frequency (RF) spectrum including at least a first RF signal of a first channel of interest and a second RF signal of a second channel of interest to at least a first second frequency signal and a second second frequency signal; a first digitizer to digitize the first second frequency signal to a first digitized signal, the first digitizer configured to operate as a low-pass analog-to-digital converter (ADC); a second digitizer to digitize the second second frequency signal to a second digitized signal, the second digitizer configured to operate as a band-pass ADC; and a digital processor to digitally process the first digitized signal and the second digitized signal.

Abstract: A signal conditioner for conditioning a differential oscillation signal into a compliant clock signal including first and second signal paths and a coincident gate. The first signal path toggles a first binary signal in response to the differential oscillation signal when the differential oscillation signal reaches a small amplitude level. The second signal path toggles a second binary signal in response to the differential oscillation signal only when the differential oscillation signal reaches a large amplitude level that is greater than the small amplitude level. The coincident gate toggles the clock signal high only when the first and second binary signals are both high, and toggles the clock signal low only when the first and second binary signals are both low. When the clock signal begins toggling, it may skip one or more cycles but is nonetheless compliant in terms of timing and amplitude.

Abstract: Method of preparing monolithic SCR catalyst with a plurality of gas flow channels comprising the steps of (a) providing a monolithic shaped substrate with a plurality of parallel gas flow channels; (b) coating the substrate with a wash coat slurry comprising vanadium oxide precursor compounds and titania and optionally tungsten oxide precursor compounds; and (c) drying the thus coated substrate with a drying rate of 5 mm/min or less along flow direction through the gas flow channels; and (d) activating the dried coated substrate by calcining.

Abstract: In one embodiment an apparatus includes: a mixer to downconvert a radio frequency (RF) spectrum including at least a first RF signal of a first channel of interest and a second RF signal of a second channel of interest to at least a first second frequency signal and a second second frequency signal; a first digitizer to digitize the first second frequency signal to a first digitized signal, the first digitizer configured to operate as a low-pass analog-to-digital converter (ADC); a second digitizer to digitize the second second frequency signal to a second digitized signal, the second digitizer configured to operate as a band-pass ADC; and a digital processor to digitally process the first digitized signal and the second digitized signal.

Abstract: A signal conditioner for conditioning a differential oscillation signal into a compliant clock signal including first and second signal paths and a coincident gate. The first signal path toggles a first binary signal in response to the differential oscillation signal when the differential oscillation signal reaches a small amplitude level. The second signal path toggles a second binary signal in response to the differential oscillation signal only when the differential oscillation signal reaches a large amplitude level that is greater than the small amplitude level. The coincident gate toggles the clock signal high only when the first and second binary signals are both high, and toggles the clock signal low only when the first and second binary signals are both low. When the clock signal begins toggling, it may skip one or more cycles but is nonetheless compliant in terms of timing and amplitude.

Abstract: Method of preparing monolithic SCR catalyst with a plurality of gas flow channels comprising the steps of (a) providing a monolithic shaped substrate with a plurality of parallel gas flow channels; (b) coating the substrate with a wash coat slurry comprising vanadium oxide precursor compounds and titania and optionally tungsten oxide precursor compounds; and (c) drying the thus coated substrate with a drying rate of 5 mm/min or less along flow direction through the gas flow channels; and (d) activating the dried coated substrate by calcining.

Abstract: Method of preparing a monolithic SCR catalyst with a plurality of gas flow channels comprising the steps of (a) providing a monolithic shaped substrate with a plurality of parallel gas flow channels; (b) coating the substrate with a washcoat slurry comprising titania; (c) drying and calcining the washcoat slurry; (d) impregnating the dried and calcined washcoat with an 10 aqueous impregnation solution comprising a precursor of a vanadium oxide; (e) drying the thus coated and impregnated washcoat at a drying rate of 5 mm/min or less along flow direction through the gas flow channels; and 15 (f) activating the dried, coated and impregnated washcoat by calcining.

Abstract: The invention relates to a novel class of serine proteases of peptidase family S2A or S1E that are stable in the presence of copper (Cu2+) and/or inhibited by copper only to a limited extent. Structural features of potential relevance for this effect are also disclosed. This class of proteases includes proteases derived from Brachysporiella gayana, Nocardiopsis dassonvillei subsp. dassonvillei, Nocardiopsis prasina, and Nocardiopsis alba, but excludes the known proteases derived from Metarhizium anisopliae and Nocardiopsis sp. NRRL 18262. The invention also relates to DNA encoding such proteases, the expression thereof in a host cell, includiThe invention relates to a novel class of serine proteases of peptidase family S2A or S1E that are stable in the presence of copper (Cu2+) and/or inhibited by copper only to a limited extent. Structural features of potential relevance for this effect are also disclosed.

Abstract: The present invention relates to acid-stable proteases of the subtilisin family, their use in animal feed, feed-additives and feed compositions containing such proteases, and methods for the treatment of vegetable proteins using such proteases.

Abstract: The present invention relates to thermostable proteases homologous to proteases derived from Nocardiopsis, and the production thereof by the wild-type, and in recombinant host cells including transgenic plants and non-human transgenic animals. The proteases are effective in animal feed, in particular fish feed, and detergents. The proteases are capable of degrading the soybean Bowman-Birk inhibitor, and other antinutritional factors such as soybean agglutinin and the Kunitz trypsin inhibitor, as well as the isolated soy storage proteins glycinin and beta-conglycinin. Characteristic structural features of relevance for the thermostability of these proteases of peptidase family S2A or S1E are disclosed.