Abstract: An active surface with a source area, a channel area and a drain area is provided in a semiconductor substrate. Each of the areas lie adjacent to a main surface of the semiconductor substrate. At least one trench is provided in the main surface of the semiconductor substrate. The trench is adjacent to the channel area and is situated in the gate electrode part. The gate electrode preferably has two opposite parts which are each adjacent to the channel area. The transistor is produced using standard process steps.

Abstract: A method and a configuration are provided for compensating for parasitic current losses in an MRAM memory cell array. Individual word lines and bit lines are supplied with currents which are proportioned in such a way that a total current level at respective points of intersection between the word lines and the bit lines is substantially constant.

Abstract: A magneto-resistive random access memory (MRAM) configuration is described in which a plurality of memory cell blocks are supplied with operating voltages that differ from one another in each case. This results in that the chip voltage supply of about 2 to 3 V can be better utilized. The memory cell blocks are formed of memory cells disposed at cross-over points of word lines and bit lines.

Abstract: A configuration for testing chips includes a printed circuit board having conductive probe needles to electrically connect the printed circuit board to chips and for testing the chips on the printed circuit board in parallel, some of the probe needles configured as dummy needles for mechanically self-aligning the chips. The board is configured closely to the application such that many chips (1) can be tested simultaneously in parallel. The chips can have markings or depressions to be engaged with free ends of the dummy needles remote from the board. Adapters can be disposed between the probe needles and the chips. Also, the chips can have structures disposed thereon between the probe needles and the chips. The board can have alignment aids for orienting the chips.

Abstract: In the method for testing a memory cell, a test voltage is applied to a memory cell and the test voltage is changed, preferably in incremental or decremental steps, during the testing. From the shape of the hysteresis of the memory cell it is determined whether or not the memory cell is a weak or substandard memory cell.

Abstract: The present invention relates to an integrated circuit which is connected to a reference-ground potential and to a supply potential. Since differing activity in the integrated circuit results in a fluctuating current being drawn by the integrated circuit, current surges may arise on the supply potential. To prevent current surges on the supply potential, a controllable load is produced together with the integrated circuit, with the result that the power drawn by the combination of integrated circuit and the load is approximately constant.

Abstract: An integrated memory has reference word lines, word lines and redundant word lines. It has a programmable activation unit whose programming state governs whether the redundant word line having redundant memory cells connected thereto replaces one of the word lines having memory cells connected thereto or the reference word line having reference cells connected thereto during operation of the memory.

Abstract: The memory cells with floating gates are tested by applying voltage surges to the source or the drain of a selection transistor.

Abstract: One electrode of each storage capacitor C of the memory cells MC is connected via the associated memory transistor T to one of the bit lines BLi and another electrode is connected to one of the plate segments PLA, PLB; PLC, PLD. A control terminal of each selection transistor T is connected to one of the word lines WLi. In a normal operating mode, the potential of only one of the plate segments in each case is pulsed in the event of accesses to the memory cells MC. In a test operating mode, the potentials of both plate segments are pulsed simultaneously.

Abstract: Memory cells are arranged at crossover points of word lines WLi and bit lines. First reference cells are arranged at crossover points of at least one first reference word line and bit lines. In a normal operating mode, the reference cells serve for generating a reference potential on the bit lines prior to a readout of the memory cells. Second reference cells are arranged at crossover points of at least one second reference word line and the bit lines. In a test operating mode, the second reference cells serve for generating a reference potential on the bit lines prior to a readout of the reference cells.

Abstract: The integrated dynamic semiconductor memory has memory cells which are combined to form individually addressable normal units and redundant units. The redundant units are used to replace faulty normal units. The address of a normal unit to be replaced is in each case stored in memory units. A self-test unit carries out a functional test of the memory cells with a defined memory-retention time for the memory cell contents, and an analysis as to which of the normal units are to be replaced by which of the redundant units. The memory units are programmed in accordance with the analysis result, and the memory-retention time is increased following the programming. The functional test, the analysis and the programming are repeated until all the memory units have been programmed. This makes it possible to achieve a high quality semiconductor memory in terms of its memory-retention time for the memory cell contents, with a comparatively low test and repair effort.

Abstract: A semiconductor memory configuration, in particular a DRAM, in which redundant memory cells, bit lines and word lines are determined for failed memory cells, failed word lines and failed bit lines by a built-in-self-test computing unit and a special algorithm.