Patents by Inventor Peter P. Cuevas

Peter P. Cuevas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7812589
    Abstract: A current source is provided with two resistor banks, and digital potentiometers are used to control how much each resistor bank affects the resulting output current. Furthermore, when the digital potentiometers are at a particular setting such that a particular resistor bank does not affect the resulting output current (i.e., the resistor bank is “inactive”), the resistance of that resistor bank can be switched without affecting the output current, thus minimizing or eliminating discontinuities in the output current during a current sweep operation. Thus, for example, when a resistor bank meets its threshold and becomes inactive, the resistance of the inactive resistor bank may be switched, and then the digital potentiometer setting may be changed to facilitate smoothly reactivating that resistor bank, with the new resistance.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: October 12, 2010
    Assignee: QualiTau, Inc.
    Inventors: James Borthwick, Peter P. Cuevas, Tal Raichman
  • Publication number: 20100052633
    Abstract: A current source is provided with two resistor banks, and digital potentiometers are used to control how much each resistor bank affects the resulting output current. Furthermore, when the digital potentiometers are at a particular setting such that a particular resistor bank does not affect the resulting output current (i.e., the resistor bank is “inactive”), the resistance of that resistor bank can be switched without affecting the output current, thus minimizing or eliminating discontinuities in the output current during a current sweep operation. Thus, for example, when a resistor bank meets its threshold and becomes inactive, the resistance of the inactive resistor bank may be switched, and then the digital potentiometer setting may be changed to facilitate smoothly reactivating that resistor bank, with the new resistance.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 4, 2010
    Applicant: QUALITAU, INC.
    Inventors: James BORTHWICK, Peter P. CUEVAS, Tal RAICHMAN
  • Patent number: 7405573
    Abstract: An interconnect assembly is for use in connection with a semiconductor device under test (DUT) having a plurality of leads to electronic test equipment. The interconnect assembly includes a cable including a plurality of wires with at least one wire for sensing a signal from a DUT, at least one wire for a forcing signal to the DUTY and at least one wire for a guarding signal driven by the same electrical potential as the forcing signal. A male connector includes the plurality of wires, an outer metal coating surrounding the plurality of wires, and an insulating coating around the outer metal coating. A receptacle connector is for receiving the male connector and plurality of wires with corresponding contacts.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: July 29, 2008
    Assignee: QualiTau, Inc.
    Inventor: Peter P. Cuevas
  • Patent number: 7172450
    Abstract: A socket for use in testing packaged integrated circuits having leads depending therefrom includes a first member for receiving the integrated circuit package and having a plurality of holes for receiving leads extending from the package. A second member has a plurality of wire contacts for engaging the leads, the first and second members being arranged to permit relative lateral translation thereof. A support frame includes a first portion which physically engages the first member and a second portion which physically engages the second member. A lever or handle is attached to the second portion and includes a cam surface for engaging a cam follower on the first portion for imparting relative lateral motion between the two members whereby the package leads physically engage wires of the second member.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: February 6, 2007
    Assignee: Qualitau, Inc.
    Inventors: Robert James Sylvia, Adalberto M. Ramirez, Jens Ullmann, Jose Ysaguirre, Peter P. Cuevas, Maurice C. Evans
  • Patent number: 7151389
    Abstract: A dual channel source measurement unit for reliability testing of electrical devices provides a voltage stress stimulus to a device under test and monitors degradation to the device under test caused by the stress simulator. The dual channel source measurement unit decouples the stress and monitor portions of the unit so that the requirements of each can be optimized. Deglitching and current clamp switches can be incorporated in the dual channel source measurement unit to prevent glitches in the switching circuitry and to limit or clamp current flow to or from the monitor and stress sources.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: December 19, 2006
    Assignee: Qualitau, Inc.
    Inventors: Tal Raichman, Peter P. Cuevas, James Borthwick, Michael A. Casolo
  • Patent number: 7098648
    Abstract: In an electrical circuit for testing electrical current using a plurality of precision resistors connected in parallel or in series, a range finder for receiving the current to be measured with the voltage drop across the range finder being indicative of a current sub-range for measurement. In a preferred embodiment, a range finder has a first bipolar transistor and a second bipolar transistor connected in parallel and in opposite polarity with the emitter and base of each transistor connected together whereby each transistor functions as an emitter-base diode.
    Type: Grant
    Filed: June 14, 2004
    Date of Patent: August 29, 2006
    Assignee: Qualitau, Inc.
    Inventors: Gedaliahoo Krieger, Peter P. Cuevas, James Borthwick
  • Patent number: 6469494
    Abstract: A programmable connector for use with a burn-in tester for manufactured integrated circuits is provided with an array of programming regions which can be selectively activated and deactivated to accommodate a specific testing configuration depending on the type of IC being tested and on the type of test being performed. The activation process is achieved using a conductive solution, applied selectively to the programming regions from a hand-held pen-type implement. The solution dries following application and serves to close a circuit between two electrically isolated conductive portions of the programming region. The solution is removable, using a solvent or other material, deactivation of the programming region for re-configuring the programmable connector.
    Type: Grant
    Filed: November 3, 1999
    Date of Patent: October 22, 2002
    Assignee: QualiTau, Inc.
    Inventor: Peter P. Cuevas
  • Patent number: 6150829
    Abstract: A three dimensional programmable connector used in a burn-in test system for manufactured integrated circuits is provided with a plurality of planar electrodes which are selectively connectable to each other and to a load board on which the integrated circuit is mounted. To implement the selective connection, programming pins are inserted in channels formed in the three-dimensional programmable connector in discrete configurations associated with various routing schemes depending on the particular wiring configuration desired, thereby enabling efficient, repeatable and cost-effective testing and analysis of the integrated circuit.
    Type: Grant
    Filed: April 5, 1999
    Date of Patent: November 21, 2000
    Assignee: Qualitau, INC
    Inventor: Peter P. Cuevas