Abstract: An inverter structure includes a p-type field effect transistor (PFET) including a PFET source, a PFET drain and a PFET gate; a n-type field effect transistor (NFET) including an NFET source, an NFET drain and an NFET gate. The NFET is adjacent to the PFET, and the PFET drain and the NFET drain form an output node and the PFET gate and the NFET gate are electrically connected to form an input node. A zero via layer includes: at least one first contact electrically coupled to the PFET source, at least one second contact electrically coupled to the NFET source, and at least one third contact electrically coupled to the output node. Each third contact has a smaller width in a fin-length direction than each first contact and each second contact to improve RC delay and overall performance.