Patents by Inventor Peter P. Waskiewicz, JR.
Peter P. Waskiewicz, JR. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230362284Abstract: Technologies for programming flexible accelerated network pipelines include a comping device with a network controller. The computing device loads a program binary file that includes a packet processing program and a requested hint section. The binary file may be an executable and linkable format (ELF) file with an extended Berkeley packet filter (eBPF) program. The computing device determines a hardware configuration for the network controller based on the requested offload hints and programs the network controller. The network controller processes network packets with the requested offloads, such as packet classification, hashing, checksums, traffic shaping, or other offloads. The network controller returns results of the offloads as hints in metadata. The packet processing program performs actions based on the metadata, such as forwarding, dropping, packet modification, or other actions. The computing device may compile an eBPF source file to generate the binary file.Type: ApplicationFiled: June 23, 2023Publication date: November 9, 2023Inventors: Peter P. WASKIEWICZ, JR., Anjali Singhai JAIN, Neerav PARIKH, Parthasarathy SARANGAM
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Patent number: 11743367Abstract: Technologies for programming flexible accelerated network pipelines include a comping device with a network controller. The computing device loads a program binary file that includes a packet processing program and a requested hint section. The binary file may be an executable and linkable format (ELF) file with an extended Berkeley packet filter (eBPF) program. The computing device determines a hardware configuration for the network controller based on the requested offload hints and programs the network controller. The network controller processes network packets with the requested offloads, such as packet classification, hashing, checksums, traffic shaping, or other offloads. The network controller returns results of the offloads as hints in metadata. The packet processing program performs actions based on the metadata, such as forwarding, dropping, packet modification, or other actions. The computing device may compile an eBPF source file to generate the binary file.Type: GrantFiled: May 10, 2022Date of Patent: August 29, 2023Assignee: Intel CorporationInventors: Peter P. Waskiewicz, Jr., Anjali Singhai Jain, Neerav Parikh, Parthasarathy Sarangam
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Publication number: 20220337682Abstract: Technologies for programming flexible accelerated network pipelines include a comping device with a network controller. The computing device loads a program binary file that includes a packet processing program and a requested hint section. The binary file may be an executable and linkable format (ELF) file with an extended Berkeley packet filter (eBPF) program. The computing device determines a hardware configuration for the network controller based on the requested offload hints and programs the network controller. The network controller processes network packets with the requested offloads, such as packet classification, hashing, checksums, traffic shaping, or other offloads. The network controller returns results of the offloads as hints in metadata. The packet processing program performs actions based on the metadata, such as forwarding, dropping, packet modification, or other actions. The computing device may compile an eBPF source file to generate the binary file.Type: ApplicationFiled: May 10, 2022Publication date: October 20, 2022Inventors: Peter P. WASKIEWICZ, JR., Anjali Singhai JAIN, Neerav PARIKH, Parthasarathy SARANGAM
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Patent number: 11336756Abstract: Technologies for programming flexible accelerated network pipelines include a comping device with a network controller. The computing device loads a program binary file that includes a packet processing program and a requested hint section. The binary file may be an executable and linkable format (ELF) file with an extended Berkeley packet filter (eBPF) program. The computing device determines a hardware configuration for the network controller based on the requested offload hints and programs the network controller. The network controller processes network packets with the requested offloads, such as packet classification, hashing, checksums, traffic shaping, or other offloads. The network controller returns results of the offloads as hints in metadata. The packet processing program performs actions based on the metadata, such as forwarding, dropping, packet modification, or other actions. The computing device may compile an eBPF source file to generate the binary file.Type: GrantFiled: September 10, 2018Date of Patent: May 17, 2022Assignee: Intel CorporationInventors: Peter P. Waskiewicz, Jr., Anjali Singhai Jain, Neerav Parikh, Parthasarathy Sarangam
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Patent number: 11102117Abstract: Methods, apparatus, and systems for implementing in Network Interface Controller (NIC) flow switching. Switching operations are effected via hardware-based forwarding mechanisms in apparatus such as NICs in a manner that does not employ use of computer system processor resources and is transparent to operating systems hosted by such computer systems. The forwarding mechanisms are configured to move or copy Media Access Control (MAC) frame data between receive (Rx) and transmit (Tx) queues associated with different NIC ports that may be on the same NIC or separate NICs. The hardware-based switching operations effect forwarding of MAC frames between NIC ports using memory operations, thus reducing external network traffic, internal interconnect traffic, and processor workload associated with packet processing.Type: GrantFiled: April 16, 2020Date of Patent: August 24, 2021Assignee: Intel CorporationInventors: Iosif Gasparakis, Peter P. Waskiewicz, Jr., Patrick Connor
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Patent number: 10990407Abstract: Methods, apparatus, and systems for facilitating effective power management through dynamic reconfiguration of interrupts. Interrupt vectors are mapped to various processor cores in a multi-core processor, and interrupt workloads on the processor cores are monitored. When an interrupt workload for a given processor core is detected to fall below a threshold, the interrupt vectors are dynamically reconfigured by remapping interrupt vectors that are currently mapped to the processor core to at least one other processor core, such that there are no interrupt vectors mapped to the processor core after reconfiguration. The core is then enabled to be put in a deeper idle state. Similar operations can be applied to additional processor cores, effecting a collapsing of interrupt vectors onto fewer processor cores.Type: GrantFiled: April 24, 2012Date of Patent: April 27, 2021Assignee: Intel CorporationInventor: Peter P. Waskiewicz, Jr.
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Publication number: 20200244577Abstract: Methods, apparatus, and systems for implementing in Network Interface Controller (NIC) flow switching. Switching operations are effected via hardware-based forwarding mechanisms in apparatus such as NICs in a manner that does not employ use of computer system processor resources and is transparent to operating systems hosted by such computer systems. The forwarding mechanisms are configured to move or copy Media Access Control (MAC) frame data between receive (Rx) and transmit (Tx) queues associated with different NIC ports that may be on the same NIC or separate NICs. The hardware-based switching operations effect forwarding of MAC frames between NIC ports using memory operations, thus reducing external network traffic, internal interconnect traffic, and processor workload associated with packet processing.Type: ApplicationFiled: April 16, 2020Publication date: July 30, 2020Applicant: Intel CorporationInventors: Iosif Gasparakis, Peter P. Waskiewicz, JR., Patrick Connor
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Patent number: 10693781Abstract: Methods, apparatus, and systems for implementing in Network Interface Controller (NIC) flow switching. Switching operations are effected via hardware-based forwarding mechanisms in apparatus such as NICs in a manner that does not employ use of computer system processor resources and is transparent to operating systems hosted by such computer systems. The forwarding mechanisms are configured to move or copy Media Access Control (MAC) frame data between receive (Rx) and transmit (Tx) queues associated with different NIC ports that may be on the same NIC or separate NICs. The hardware-based switching operations effect forwarding of MAC frames between NIC ports using memory operations, thus reducing external network traffic, internal interconnect traffic, and processor workload associated with packet processing.Type: GrantFiled: November 3, 2015Date of Patent: June 23, 2020Assignee: Intel CorporationInventors: Iosif Gasparakis, Peter P. Waskiewicz, Jr., Patrick Connor
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Patent number: 10530880Abstract: Scalable multi-tenant networking can preserve segregation of traffic of different tenants across multiple VLANs over a cluster of nodes. A single process is bound to a wildcard address and a port to listen for traffic across the VLANs and the cluster of nodes. The process detects receipt of a request at one of the multiple addresses assigned to the multiple VLANs and resolves the address to a name of a corresponding one of the VLANs. This is then used to determine an address of a node that is part of the VLAN and that hosts a volume identified in the received request. The requesting client is then redirected to the node that is part of the VLAN and that hosts the identified volume.Type: GrantFiled: October 31, 2014Date of Patent: January 7, 2020Assignee: NetApp, Inc.Inventors: Marshall McMullen, Peter P. Waskiewicz, Jr.
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Patent number: 10382343Abstract: Data traffic of different customers or tenants can be efficiently handled at a shared node while still being isolated from each other. An application instance can create multiple network stack that are isolated from each other and intelligently manage threads across the isolated network stack instances. To intelligently manage the threads across the network stack instances, each thread maintains data that identifies the network stack to which the thread is assigned. With this information, the application can intelligently use a thread already assigned to a network stack that will process the data traffic and avoid the performance impact of a system call to assign the thread to the network stack.Type: GrantFiled: June 1, 2017Date of Patent: August 13, 2019Assignee: NetApp, Inc.Inventors: Peter P. Waskiewicz, Jr., Jared Cantwell, Marshall McMullen, Carl Jeffrey Seelye
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Publication number: 20180287951Abstract: Data traffic of different customers or tenants can be efficiently handled at a shared node while still being isolated from each other. An application instance can create multiple network stack that are isolated from each other and intelligently manage threads across the isolated network stack instances. To intelligently manage the threads across the network stack instances, each thread maintains data that identifies the network stack to which the thread is assigned. With this information, the application can intelligently use a thread already assigned to a network stack that will process the data traffic and avoid the performance impact of a system call to assign the thread to the network stack.Type: ApplicationFiled: June 1, 2017Publication date: October 4, 2018Inventors: Peter P. Waskiewicz, JR., Jared Cantwell, Marshall McMullen, Carl Jeffrey Seelye
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Patent number: 9537827Abstract: A method includes binding, using a plurality of processors, a process to a wildcard address and a port on each of a plurality of nodes. The process receives, on a redirector node, a first request for a first address of a first volume located on the cluster from a first client. The first request is sent to the port and a first address associated with a first virtual local area network (VLAN) that is not the wildcard address. The process determines the first address from the first request and a name of the first VLAN based on the first address. The process determines a first node that contains information regarding the first volume and an address of the first node that is part of the first VLAN. The process determines that a volume identifier associated with the first volume of the first request is present on a volume list.Type: GrantFiled: December 21, 2015Date of Patent: January 3, 2017Assignee: NETAPP, INC.Inventors: Marshall McMullen, Peter P. Waskiewicz, Jr., Derek Leslie
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Patent number: 9411725Abstract: Described are embodiments of mediums, methods, and systems for application-reserved use of cache for direct I/O. A method for using application-reserved cache may include reserving, by one of a plurality of cores of a processor, use of a first portion of one of a plurality of levels of cache for an application executed by the one of the plurality of cores, and transferring, by the one of the plurality of cores, data associated with the application from an input/output (I/O) device of a computing device directly to the first portion of the one of the plurality of levels of the cache. Other embodiments may be described and claimed.Type: GrantFiled: March 22, 2012Date of Patent: August 9, 2016Assignee: Intel CorporationInventors: Iosif Gasparakis, Peter P. Waskiewicz, Jr.
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Publication number: 20160057056Abstract: Methods, apparatus, and systems for implementing in Network Interface Controller (NIC) flow switching. Switching operations are effected via hardware-based forwarding mechanisms in apparatus such as NICs in a manner that does not employ use of computer system processor resources and is transparent to operating systems hosted by such computer systems. The forwarding mechanisms are configured to move or copy Media Access Control (MAC) frame data between receive (Rx) and transmit (Tx) queues associated with different NIC ports that may be on the same NIC or separate NICs. The hardware-based switching operations effect forwarding of MAC frames between NIC ports using memory operations, thus reducing external network traffic, internal interconnect traffic, and processor workload associated with packet processing.Type: ApplicationFiled: November 3, 2015Publication date: February 25, 2016Applicant: Intel CorporationInventors: Iosif Gasparakis, Peter P. Waskiewicz, JR., Patrick Connor
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Patent number: 9225801Abstract: Methods, systems, and apparatuses, including computer programs encoded on computer-readable media are disclosed for binding a process to a wildcard address and a port on a plurality of nodes of a cluster. A process receives a first request for a first address of a first volume that is sent to the port and a first address associated with a first virtual local area network that is not the wildcard address. The process determines the first address, a name of the first VLAN, and a first node that contains information regarding the first volume. The process determines an address of the first node that is part of the first VLAN. The address of the first node is returned. The process receives another request for a second address of a second volume that is sent to the port and a second address associated with another VLAN that is not the wildcard address.Type: GrantFiled: April 13, 2015Date of Patent: December 29, 2015Assignee: SolidFire, Inc.Inventors: Marshall McMullen, Peter P. Waskiewicz, Jr.
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Patent number: 9112602Abstract: Automatically determining a link speed between link partners using a multispeed fiber module. An embodiment solves the problem of how to determine the highest common link speed between short range (SR)/long range (LR) fiber link partners when at least one of the link partners is using a multispeed fiber module. In an embodiment, a multispeed fiber module comprises a module that is capable of both 10 gigabit (GB) per second Ethernet and 1 GB per second Ethernet or lesser data transfer speeds over a fiber optical link. In an embodiment, the method comprises trying each link speed in a known succession, from highest supported speed to lowest supported speed. In an embodiment, an initiator link partner “blinks” a transmit laser, which alerts the link partners that a link speed determination session is being initiated. By automatically determining link speed, the user is relieved of the necessity to manually configure the link speed.Type: GrantFiled: June 25, 2010Date of Patent: August 18, 2015Assignee: Intel CorporationInventors: Aaron K. Salter, Peter P. Waskiewicz, Jr., Scott P. Dubal, Brian Kantor
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Publication number: 20140059170Abstract: Examples are disclosed for a device having at least two media access controllers. In some examples, a first media access controller may be coupled to a host computing device. A second media access controller may be coupled to one or more processor circuits arranged to perform packet processing of data payloads for one or more data frames forwarded through the first media access controller and/or forwarded through the second media access controller. The first media access controller may be coupled to the second media access controller via a communication link. Other examples are described and claimed.Type: ApplicationFiled: May 2, 2012Publication date: February 27, 2014Inventors: Iosif Gasparakis, Peter P. Waskiewicz, JR., Ilango S. Ganga, Terry V. Hulett, Parathasarathy Sarangam
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Publication number: 20140059225Abstract: Generally, this disclosure describes a network controller for remote system management. A host device may include the network controller and a programmable network element. The network controller may include controller circuitry configured to acquire network management data related to operation of the network controller and to receive host management data related to operation of the host device. The network controller may further include a transmitter configured to transmit the network and host management data to a management system remote from the network controller and a receiver configured to receive a command from the management system related to the management data, the command configured to reprogram the programmable network element to change a behavior of the programmable network element.Type: ApplicationFiled: August 21, 2012Publication date: February 27, 2014Inventors: Iosif Gasparakis, Ilango S. Ganga, Peter P. Waskiewicz, JR.
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Publication number: 20130318303Abstract: Described are embodiments of mediums, methods, and systems for application-reserved use of cache for direct I/O. A method for using application-reserved cache may include reserving, by one of a plurality of cores of a processor, use of a first portion of one of a plurality of levels of cache for an application executed by the one of the plurality of cores, and transferring, by the one of the plurality of cores, data associated with the application from an input/output (I/O) device of a computing device directly to the first portion of the one of the plurality of levels of the cache. Other embodiments may be described and claimed.Type: ApplicationFiled: March 22, 2012Publication date: November 28, 2013Inventors: Iosif Gasparakis, Peter P. Waskiewicz, JR.
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Publication number: 20130318334Abstract: Methods, apparatus, and systems for facilitating effective power management through dynamic reconfiguration of interrupts. Interrupt vectors are mapped to various processor cores in a multi-core processor, and interrupt workloads on the processor cores are monitored. When an interrupt workload for a given processor core is detected to fall below a threshold, the interrupt vectors are dynamically reconfigured by remapping interrupt vectors that are currently mapped to the processor core to at least one other processor core, such that there are no interrupt vectors mapped to the processor core after reconfiguration. The core is then enabled to be put in a deeper idle state. Similar operations can be applied to additional processor cores, effecting a collapsing of interrupt vectors onto fewer processor cores.Type: ApplicationFiled: April 24, 2012Publication date: November 28, 2013Inventor: Peter P. Waskiewicz, JR.