Patents by Inventor Peter Paneah
Peter Paneah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230353419Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.Type: ApplicationFiled: July 9, 2023Publication date: November 2, 2023Inventors: Daniel Marcovitch, Idan Burstein, Liran Liss, Hillel Chapman, Dror Goldenberg, Michael Kagan, Aviad Yehezkel, Peter Paneah
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Patent number: 11750418Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.Type: GrantFiled: September 7, 2020Date of Patent: September 5, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Daniel Marcovitch, Idan Burstein, Liran Liss, Hillel Chapman, Dror Goldenberg, Michael Kagan, Aviad Yehezkel, Peter Paneah
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Publication number: 20230214341Abstract: Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.Type: ApplicationFiled: February 27, 2023Publication date: July 6, 2023Inventors: Tzahi Oved, Achiad Shochat, Liran Liss, Noam Bloch, Aviv Heller, Idan Burstein, Ariel Shahar, Peter Paneah
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Patent number: 11620245Abstract: Computing apparatus includes a host computer, including at least first and second host bus interfaces. A network interface controller (NIC) includes a network port, for connection to a packet communication network, and first and second NIC bus interfaces, which communicate via first and second peripheral component buses with the first and second host bus interfaces, respectively. Packet processing logic, in response to packets received through the network port, writes data to the host memory concurrently via both the first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions, and after writing the data in any given DMA transaction, writes a completion report to the host memory with respect to the given DMA transaction while verifying that the completion report will be available to the CPU only after all the data in the given DMA transaction have been written to the host memory.Type: GrantFiled: October 18, 2021Date of Patent: April 4, 2023Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Tzahi Oved, Achiad Shochat, Liran Liss, Noam Bloch, Aviv Heller, Idan Burstein, Ariel Shahar, Peter Paneah
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Patent number: 11500808Abstract: A peripheral device includes a bus interface and circuitry. The bus interface is configured to connect to a peripheral bus for communicating with a host in accordance with a peripheral-bus specification that specifies a physical reset signal asserted by the host. The circuitry is configured to execute predefined logic that evaluates a reset condition that is indicative of imminent assertion of the physical reset signal by the host, and to perform a reset procedure in response to meeting the reset condition.Type: GrantFiled: July 26, 2021Date of Patent: November 15, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Avraham Ganor, Peter Paneah, Dotan David Levi
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Publication number: 20220358063Abstract: Computing apparatus includes a host computer, including at least first and second host bus interfaces. A network interface controller (NIC) includes a network port, for connection to a packet communication network, and first and second NIC bus interfaces, which communicate via first and second peripheral component buses with the first and second host bus interfaces, respectively. Packet processing logic, in response to packets received through the network port, writes data to the host memory concurrently via both the first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions, and after writing the data in any given DMA transaction, writes a completion report to the host memory with respect to the given DMA transaction while verifying that the completion report will be available to the CPU only after all the data in the given DMA transaction have been written to the host memory.Type: ApplicationFiled: October 18, 2021Publication date: November 10, 2022Inventors: Tzahi Oved, Achiad Shochat, Liran Liss, Noam Bloch, Aviv Heller, Idan Burstein, Ariel Shahar, Peter Paneah
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Publication number: 20220078043Abstract: A cross-network bridging apparatus includes a bus interface and bridging circuitry. The bus interface is configured for connecting to a system bus. The bridging circuitry is configured to translate between (i) system-bus transactions that are exchanged between one or more local devices that are coupled to the system bus and served by the system bus and one or more remote processors located across a network from the apparatus, and (ii) data units that convey the system-bus transactions, for transmitting and receiving as network packets over the network to and from the remote processors.Type: ApplicationFiled: September 7, 2020Publication date: March 10, 2022Inventors: Daniel Marcovitch, Idan Burstein, Liran Liss, Hillel Chapman, Dror Goldenberg, Michael Kagan, Aviad Yehezkel, Peter Paneah
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Publication number: 20220075747Abstract: A networking device, system, and method of operating a networking device are provided. The illustrative networking device is disclosed to include one or more physical ports, an emulated switch positioned between the one or more physical ports and a host device, and one or more emulated devices positioned between the emulated switch and the one or more physical ports. The one or more emulated devices may be configured to populate the one or more physical ports.Type: ApplicationFiled: September 9, 2020Publication date: March 10, 2022Inventors: Shahaf Shuler, Peter Paneah, Tzuriel Katoa
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Patent number: 11218397Abstract: An apparatus includes a processor, a first interface configured to connect to a bus of the apparatus, a second interface configured to communicate over a packet network, and circuitry. The circuitry is configured to, in a first operational mode, exchange data between the processor and one or more remote devices over the packet network, via the second interface, and in a second operational mode, monitor the bus using the first interface, detect a predefined trigger event occurring on the bus and, in response to detecting the trigger event, log one or more transactions on the bus that are adjacent to the trigger event and generate one or more protocol-analysis packets comprising at least part of the logged transactions.Type: GrantFiled: January 27, 2019Date of Patent: January 4, 2022Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Peter Paneah, Yoni Galezer, Vladimir Vainer
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Patent number: 10887252Abstract: A network interface device is connected to a host computer by having a memory controller, and a scatter-gather offload engine linked to the memory controller. The network interface device prepares a descriptor including a plurality of specified memory locations in the host computer, incorporates the descriptor in exactly one upload packet, transmits the upload packet to the scatter-gather offload engine via the uplink, invokes the scatter-gather offload engine to perform memory access operations cooperatively with the memory controller at the specified memory locations of the descriptor, and accepts results of the memory access operations.Type: GrantFiled: November 6, 2018Date of Patent: January 5, 2021Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Dror Bohrer, Noam Bloch, Peter Paneah, Richard Graham
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Patent number: 10852967Abstract: Apparatuses and methods are described that provide for a mechanism for allocating physical device memory for one or more virtual functions. In particular, a memory allocating framework is provided to utilize device memory more efficiently by mapping at least one target location of the physical memory in a Base Address Register (BAR) associated with the virtual function from a plurality of available target locations based on an allocation request. The memory allocating framework is further configured to compare an indication associated with the requesting virtual function to an identifier of the requested target location. Moreover, the memory allocating framework is further configured to allow the simultaneous use of more than one virtual function at a time while providing isolation between multiple virtual functions.Type: GrantFiled: April 26, 2018Date of Patent: December 1, 2020Assignee: Mellanox Technologies, Ltd.Inventors: Ariel Shahar, Peter Paneah, Maxim Zaborov
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Patent number: 10802982Abstract: An apparatus includes an interface and memory acquisition circuitry. The interface is configured to communicate over a bus operating in accordance with a bus protocol, which supports address-translation transactions that translate between bus addresses in an address space of the bus and physical memory addresses in an address space of a memory. The memory acquisition circuitry is configured to read data from the memory by issuing over the bus, using the bus protocol, one or more requests that (i) specify addresses to be read in terms of the physical memory addresses, and (ii) indicate that the physical memory addresses in the requests have been translated from corresponding bus addresses even though the addresses were not obtained by any address-translation transaction over the bus.Type: GrantFiled: April 8, 2018Date of Patent: October 13, 2020Assignee: MELLANOX TECHNOLOGIES, LTD.Inventors: Ahmad Atamlh, Ofir Arkin, Peter Paneah
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Publication number: 20200244562Abstract: An apparatus includes a processor, a first interface configured to connect to a bus of the apparatus, a second interface configured to communicate over a packet network, and circuitry. The circuitry is configured to, in a first operational mode, exchange data between the processor and one or more remote devices over the packet network, via the second interface, and in a second operational mode, monitor the bus using the first interface, detect a predefined trigger event occurring on the bus and, in response to detecting the trigger event, log one or more transactions on the bus that are adjacent to the trigger event and generate one or more protocol-analysis packets comprising at least part of the logged transactions.Type: ApplicationFiled: January 27, 2019Publication date: July 30, 2020Inventors: Peter Paneah, Yoni Galezer, Vladimir Vainer
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Publication number: 20190332291Abstract: Apparatuses and methods are described that provide for a mechanism for allocating physical device memory for one or more virtual functions. In particular, a memory allocating framework is provided to utilize device memory more efficiently by mapping at least one target location of the physical memory in a Base Address Register (BAR) associated with the virtual function from a plurality of available target locations based on an allocation request. The memory allocating framework is further configured to compare an indication associated with the requesting virtual function to an identifier of the requested target location. Moreover, the memory allocating framework is further configured to allow the simultaneous use of more than one virtual function at a time while providing isolation between multiple virtual functions.Type: ApplicationFiled: April 26, 2018Publication date: October 31, 2019Inventors: Ariel Shahar, Peter Paneah, Maxim ZABOROV
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Publication number: 20190310945Abstract: An apparatus includes an interface and memory acquisition circuitry. The interface is configured to communicate over a bus operating in accordance with a bus protocol, which supports address-translation transactions that translate between bus addresses in an address space of the bus and physical memory addresses in an address space of a memory. The memory acquisition circuitry is configured to read data from the memory by issuing over the bus, using the bus protocol, one or more requests that (i) specify addresses to be read in terms of the physical memory addresses, and (ii) indicate that the physical memory addresses in the requests have been translated from corresponding bus addresses even though the addresses were not obtained by any address-translation transaction over the bus.Type: ApplicationFiled: April 8, 2018Publication date: October 10, 2019Inventors: Ahmad Atamlh, Ofir Arkin, Peter Paneah
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Patent number: 10394747Abstract: A computing system comprises one or more cores. Each core comprises a processor. In some implementations, each processor is coupled to a communication network among the cores. In some implementations, a switch in each core includes switching circuitry to forward data received over data paths from other cores to the processor and to switches of other cores, and to forward data received from the processor to switches of other cores. Also disclosed are techniques for implementing hierarchical serial interconnects such as a PCI Express switch topology over a coherent mesh interconnect.Type: GrantFiled: May 31, 2017Date of Patent: August 27, 2019Assignee: Mellanox Technologies Ltd.Inventors: Peter Paneah, Carl G. Ramey, Gil Moran, Adi Menachem, Christopher J. Jackson, Ilan Pardo, Ariel Shahar, Tzuriel Katoa
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Publication number: 20190149486Abstract: A network interface device is connected to a host computer by having a memory controller, and a scatter-gather offload engine linked to the memory controller. The network interface device prepares a descriptor including a plurality of specified memory locations in the host computer, incorporates the descriptor in exactly one upload packet, transmits the upload packet to the scatter-gather offload engine via the uplink, invokes the scatter-gather offload engine to perform memory access operations cooperatively with the memory controller at the specified memory locations of the descriptor, and accepts results of the memory access operations.Type: ApplicationFiled: November 6, 2018Publication date: May 16, 2019Inventors: Dror Bohrer, Noam Bloch, Peter Paneah, Richard Graham
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Patent number: 8365057Abstract: A network communication device includes a host interface, which is coupled to communicate with a host processor, having a memory, so as to receive a work request to convey one or more data blocks over a network. The work request specifies a memory region of a given data size, and at least one data integrity field (DIF), having a given field size, is associated with the data blocks. Network interface circuitry is configured to execute an input/output (I/O) data transfer operation responsively to the work request so as to transfer to or from the memory a quantity of data that differs from the data size of the memory region by a multiple of the field size, while adding the at least one DIF to the transferred data or removing the at least one DIF from the transferred data.Type: GrantFiled: July 30, 2009Date of Patent: January 29, 2013Assignee: Mellanox Technologies LtdInventors: Dror Goldenberg, Hillel Chapman, Achiad Shochat, Peter Paneah, Tamir Azarzar, Dror Bohrer, Michael Kagan
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Publication number: 20110029847Abstract: A network communication device includes a host interface, which is coupled to communicate with a host processor, having a memory, so as to receive a work request to convey one or more data blocks over a network. The work request specifies a memory region of a given data size, and at least one data integrity field (DIF), having a given field size, is associated with the data blocks. Network interface circuitry is configured to execute an input/output (I/O) data transfer operation responsively to the work request so as to transfer to or from the memory a quantity of data that differs from the data size of the memory region by a multiple of the field size, while adding the at least one DIF to the transferred data or removing the at least one DIF from the transferred data.Type: ApplicationFiled: July 30, 2009Publication date: February 3, 2011Applicant: MELLANOX TECHNOLOGIES LTDInventors: Dror Goldenberg, Hillel Chapman, Achiad Shochat, Peter Paneah, Tamir Azarzar, Dror Bohrer, Michael Kagan
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Publication number: 20040218623Abstract: A network interface adapter includes a memory interface, for coupling to a memory containing a first data packet composed in accordance with a first communication protocol, and a network interface, for coupling to a packet communication network. Packet processing circuitry in the adapter reads the first data packet from the memory via the memory interface, computes a checksum of the first data packet, inserts the checksum in the first data packet in accordance with the first communication protocol, and encapsulates the first data packet in a payload of a second data packet in accordance with a second communication protocol applicable to the packet communication network, so as to transmit the second data packet over the network via the network interface. The circuitry likewise computes checksums of incoming encapsulated data packets from the network.Type: ApplicationFiled: May 1, 2003Publication date: November 4, 2004Inventors: Dror Goldenberg, Michael Kagan, Benny Koren, Gil Stoler, Peter Paneah, Roi Rachamim, Gilad Shainer, Rony Gutierrez, Sagi Rotem, Dror Bohrer