Patents by Inventor Peter Pani

Peter Pani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070268041
    Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect substantially a first plurality of conductors, through a first set of switches, to a second plurality sets of conductors. The conductors in each set of the second plurality of conductors substantially connect, through a second set of switches, to a third plurality of sets of conductors. Each conductor of a set of the third plurality sets of conductors either connects, physically, to one pin in each of a plurality of functional blocks or, through a third set of switches, to a subsequent fourth set of conductors. The SN is scalable for larger sets of conductors by adding additional sets of intermediate conductors in a hierarchically fashion.
    Type: Application
    Filed: June 26, 2007
    Publication date: November 22, 2007
    Inventors: Peter Pani, Benjamin Ting
  • Publication number: 20070236250
    Abstract: An interconnection fabric using switching networks organized in multiple levels of hierarchy to allow flexible interconnections of the switching networks amongst different levels of hierarchy and on the same level of hierarchy. The resulting interconnection fabric can be used in electronic devices, such as switching networks, routers, and programmable logic circuits, etc.
    Type: Application
    Filed: March 28, 2006
    Publication date: October 11, 2007
    Inventors: Peter Pani, Benjamin Ting
  • Publication number: 20060202716
    Abstract: An integrated circuit including a programmable logic array with a plurality of logic cells and programmable interconnections to receive input signals and to perform logical functions to transmit output signals. The integrated circuit may also include megacells comprising a plurality of functional blocks receiving inputs and transmitting outputs. The integrated circuit may also include a programmable interconnections subsystem to cascade the megacells. The megacells are coupled to the programmable logic array.
    Type: Application
    Filed: September 1, 2005
    Publication date: September 14, 2006
    Inventors: Peter Pani, Benjamin Ting
  • Publication number: 20060114023
    Abstract: A multiple level routing architecture for a programmable logic device having logical blocks, each logical block comprising a plurality of cells, with a first level routing resources coupling the cells of logical blocks. A second level routing resources coupling the first level routing resources through tab networks; each tab network comprises a first plurality of switches coupling the first level routing resources to an intermediate tab and the intermediate tab coupling the second level routing resources through a second plurality of switches, each switch may comprise an additional buffer. Repeated applications of tab networks provide connections between lower level routing resources to higher level routing resources.
    Type: Application
    Filed: January 4, 2006
    Publication date: June 1, 2006
    Inventors: Benjamin Ting, Peter Pani
  • Publication number: 20060023704
    Abstract: An interconnection fabric using switching networks hierarchically to allow interconnections of large number of a first plurality of conductors to a large number of k plurality of conductors is described. The resulting interconnection fabric can be used in switching networks, routers and programmable logic circuits.
    Type: Application
    Filed: July 29, 2004
    Publication date: February 2, 2006
    Inventors: Peter Pani, Benjamin Ting
  • Publication number: 20060006906
    Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of) conductors that are used to connect substantially a first plurality of conductors, through a first set of switches, to a second plurality sets of conductors. The conductors in each set of the second plurality of conductors substantially connect, through a second set of switches, to a third plurality of sets of conductors. Each conductor of a set of the third plurality sets of conductors either connects, physically, to one pin in each of a plurality of functional blocks or, through a third set of switches, to a subsequent fourth plurality sets of conductors. The SN is scalable for large sized sets of conductors and can be used hierarchically in, for example, an integrated circuit or in an electronic system.
    Type: Application
    Filed: September 1, 2005
    Publication date: January 12, 2006
    Inventors: Peter Pani, Benjamin Ting
  • Publication number: 20050218928
    Abstract: A scalable non-blocking switching network (SN) having switches and intermediate (stages of ) conductors that are used to connect a first plurality of conductors to other multiple sets of conductors in a generally unrestricted fashion within respective interconnect resources constraints. The SN can be applied in a wide range of applications, in tandem or hierarchically, to provide a large switch network used in network, routers, and programmable logic circuits. The SN is used to connect a first set of conductors, through the SN, to multiple sets of conductors in a given logic circuit hierarchy whereby the conductors in each of the multiple sets are equivalent or exchangeable, which in term, by construction, makes the first set of conductors equivalent when used in the next level of circuit hierarchy. The SN is scalable for large sized sets of conductors and can be used hierarchically to enable programmable interconnections among large sized circuits.
    Type: Application
    Filed: March 30, 2004
    Publication date: October 6, 2005
    Inventors: Peter Pani, Benjamin Ting