Patents by Inventor Peter Paterson

Peter Paterson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Managing access of multiple executing programs to non-local block data storage
    Patent number: 12223182
    Abstract: Techniques are described for managing access of executing programs to non-local block data storage. In some situations, a block data storage service uses multiple server storage systems to reliably store network-accessible block data storage volumes that may be used by programs executing on other physical computing systems. A group of multiple server block data storage systems that store block data volumes may in some situations be co-located at a data center, and programs that use volumes stored there may execute on other physical computing systems at that data center. If a program using a volume becomes unavailable, another program (e.g., another copy of the same program) may in some situations obtain access to and continue to use the same volume, such as in an automatic manner in some such situations.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: February 11, 2025
    Assignee: Amazon Technologies, Inc.
    Inventors: Roland Paterson-Jones, Peter N. DeSantis, Atle Normann Jorgensen, Matthew S. Garman, Tate Andrew Certain
  • Blocked based design methodology
    Patent number: 6725432
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: April 20, 2004
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Block based design methodology
    Patent number: 6701504
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: March 2, 2004
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Blocked based design methodology
    Patent number: 6698002
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: February 24, 2004
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Block based design methodology
    Patent number: 6694501
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: February 17, 2004
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Block based design methodology
    Patent number: 6631470
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: October 7, 2003
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Block based design methodology
    Patent number: 6629293
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: September 30, 2003
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Block based design methodology
    Patent number: 6594800
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: July 15, 2003
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Block based design methodology
    Publication number: 20030115564
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Application
    Filed: March 23, 2001
    Publication date: June 19, 2003
    Applicant: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Block based design methodology
    Patent number: 6574778
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: June 3, 2003
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Block based design methodology
    Patent number: 6567957
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: May 20, 2003
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Block based design methodology
    Publication number: 20020166098
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Application
    Filed: March 23, 2001
    Publication date: November 7, 2002
    Applicant: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Block based design methodology
    Publication number: 20020016952
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Application
    Filed: January 4, 2001
    Publication date: February 7, 2002
    Applicant: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Block based design methodology
    Publication number: 20010042237
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Application
    Filed: February 23, 2001
    Publication date: November 15, 2001
    Applicant: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Block based design methodology
    Publication number: 20010039641
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Application
    Filed: March 23, 2001
    Publication date: November 8, 2001
    Applicant: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Block based design methodology
    Publication number: 20010025369
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Application
    Filed: January 4, 2001
    Publication date: September 27, 2001
    Applicant: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Block based design methodology
    Publication number: 20010018756
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Application
    Filed: January 4, 2001
    Publication date: August 30, 2001
    Applicant: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Block based design methodology
    Publication number: 20010016933
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Application
    Filed: January 4, 2001
    Publication date: August 23, 2001
    Applicant: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani
  • Block based design methodology
    Patent number: 6269467
    Abstract: A method and apparatus for designing a circuit system, including selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, collecting data reflecting the experience of the designer regarding the pre-designed circuit blocks, the designer's experience being adaptable to a processing method, accepting or rejecting a design of the circuit system in a manner based on the designer's experience data and acceptable degree of risk, upon acceptance, forming block specifications containing criteria and modified constraints for each of the circuit blocks, upon acceptance, forming block specifications for deploying the circuit blocks on a floor plan of a chip, as a system on a chip, in compliance with the criteria and modified constraints, and substantially without changing the selected circuit block and the processing method.
    Type: Grant
    Filed: September 30, 1999
    Date of Patent: July 31, 2001
    Assignee: Cadence Design Systems, Inc.
    Inventors: Henry Chang, Larry Cooke, Merrill Hunt, Wuudiann Ke, Christopher K. Lennard, Grant Martin, Peter Paterson, Khoan Truong, Kumar Venkatramani