Abstract: This disclosure describes systems, methods, and devices for placing bits in an isochronous data stream from a first data port to a second data port. A device may inject, using a first port, based on a periodicity less than a defined frame rate of a data stream comprising multiple frames, a status or control bit in place of one or more low-order bits, reserved bits, or unused bits of a frame of the data stream, wherein the frame includes one or more data words; receive, using a second port synchronized to the periodicity, the data stream from the first port; extract, using the second port, based on the periodicity, the status or control bit; and extract, using the second port, a remainder of the frame.

Abstract: A radio frequency front end device includes an antenna interface, configured to receive a signal representing a radio transmission; a radio frequency detector, wherein the signal includes a first signal in a first frequency range and a second signal in a second frequency range, adjacent to the first frequency range, and wherein the radio frequency detector is configured to detect the second signal within the second frequency range; and a processor, configured to select, based on the second signal, a sampling window size for a sampling window of a signal windowing procedure for the first signal in the first frequency range; and implement the signal windowing procedure on the first signal at the sampling window size.

Abstract: Disclosed herein are antenna systems, methods, and devices. The device includes a first portion including a first antenna array; and a second portion including a second antenna array, wherein the first portion and the second portion are movable with respect to one another, and wherein the first antenna array and the second antenna array are arranged such that in a first relative position of the first portion and the second portion with respect to one another the first antenna array and the second antenna array operate in combination with one another, and in a second relative position of the first portion and the second portion with respect to one another the first antenna array and the second antenna array operate independently of one another.

Abstract: A method and apparatus for automatic gain control (AGC). A transceiver includes an analog-to-digital converter (ADC) configured to convert a received analog signal to digital signal, a measurement circuitry configured to measure a signal level on the digital signal, an AGC controller configured to generate, based on the measured signal level, an analog gain control signal to change a gain to be applied to a received analog signal in analog domain and a digital gain control signal for digital gain compensation corresponding to the gain change in analog domain, and a digital gain compensation circuitry configured to apply the digital gain compensation based on the digital gain control signal. The digital compensation gain applied to the digital bits follows a ramp profile that is an inverse of a transient response to the gain change in analog domain.

Abstract: An apparatus can include baseband processing circuitry to generate at least one artificial channel function for combining with at least one multiple-input multiple-output (MIMO) layer input to a precoder. The baseband processing circuitry can also provide the combined artificial channel function and MIMO layer input to the precoder. The apparatus can also include circuitry to transmit a channel based on the combined artificial channel function and MIMO layer input. Other systems and methods are also described.

Abstract: A wireless communication device can include modem circuitry to connect the UE to a repeater over a side-link connection. The device can also include processing circuitry to control a repeater beamforming process to select a beam angle from the repeater to a base station and initiate a communication procedure using the selected beam angle. Other methods, systems and apparatuses are described.

Abstract: An apparatus for transmitting output signals includes a pre-distortion circuit configured to perform digital pre-distortion (DPD) on input signal samples using a plurality of DPD coefficients to generate a plurality of pre-distorted samples. The apparatus further includes an estimation window search circuit configured to determine a signal power characteristic for each pre-distorted sample of the plurality of pre-distorted samples, and select a subset of the plurality of pre-distorted samples based on the determined signal power characteristics. The subset of the plurality of pre-distorted samples is selected to fit within a predetermined estimation window size. The plurality of DPD coefficients is updated based on the subset of the plurality of pre-distorted samples.

Abstract: In a communication device and corresponding methods, a hierarchical, reduced power, beam search process includes a hierarchical activation of the radio frequency frontend (RFFE), transceiver, and baseband integrated circuit (BBIC) for a beam searching operations. For example, a first signal metric measurements can be performed to determine signal information. An operating mode can be determined based on the signal information. In a first operating mode, one or more second signal metric measurements can be performed for a subset of beamforming configurations of the wireless communication device to determine beamforming information. In a second operating mode, one or more third signal metric measurements can be performed on the beamforming configurations to determine the beamforming information.

Abstract: Techniques are described related to digital radio control, partitioning, and operation. The various techniques described herein enable high-frequency local oscillator signal generation and frequency multiplication using radio-frequency (RF) digital to analog converters (RFDACs). The use of these components and others described throughout this disclosure allow for the realization of various improvements. For example, digital, analog, and hybrid beamforming control are implemented and the newly-enabled digital radio architecture partitioning enables radio components to be pushed to the radio head, allowing for the omission of high frequency cables and/or connectors.

Abstract: In a communication device and corresponding methods, a hierarchical, reduced power, beam search process includes a hierarchical activation of the radio frequency frontend (RFFE), transceiver, and baseband integrated circuit (BBIC) for a beam searching operations. For example, a first signal metric measurements can be performed to determine signal information. An operating mode can be determined based on the signal information. In a first operating mode, one or more second signal metric measurements can be performed for a subset of beamforming configurations of the wireless communication device to determine beamforming information. In a second operating mode, one or more third signal metric measurements can be performed on the beamforming configurations to determine the beamforming information.

Abstract: Sequence trigger circuitry may be configured to repeat command sequences to switch between communication modes of a RFFE. The circuitry may include a first logic circuitry to, in response to a trigger signal, generate a first output signal or a second output signal to activate a first command sequence or a second command sequence, respectively. The circuitry may also include a second logic circuitry to activate a third command sequence based on a comparison of a clock output signal with a first timer value and upon generating the first output signal. The first command sequence and the third command sequence may switch the RFFE into a receive mode of the plurality of modes. The circuitry may include a third logic circuitry to activate a fourth command sequence based on a comparison of the clock output signal with a second timer value and upon generating the second output signal.

Abstract: Sequence trigger circuitry may be configured to repeat command sequences to switch between communication modes of a RFFE. The circuitry may include a first logic circuitry to, in response to a trigger signal, generate a first output signal or a second output signal to activate a first command sequence or a second command sequence, respectively. The circuitry may also include a second logic circuitry to activate a third command sequence based on a comparison of a clock output signal with a first timer value and upon generating the first output signal. The first command sequence and the third command sequence may switch the RFFE into a receive mode of the plurality of modes. The circuitry may include a third logic circuitry to activate a fourth command sequence based on a comparison of the clock output signal with a second timer value and upon generating the second output signal.