Patents by Inventor Peter Pirsch

Peter Pirsch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4827340
    Abstract: For a video-signal-coding facility using adaptive DPCM in which switching is effected block by block between different predictors, a basic circuit arrangement is given for the case where switching is to be effected between a two-dimensional intraframe predictor and a pure interframe predictor (FIG. 1). Uniform processor elements (PE.sub.1, PE.sub.0) cooperate with predictor loops (Pr.sub.1, Pr.sub.2, 10, 11) and circuits are provided which ensure that the appropriate reconstructed sample values (X.sub.0 ', X.sub.1 ') are used whenever switching between coders occurs. In a preferred embodiment (FIG. 3), the decision on the best suited coder is delayed by one block, whereby the maximum processing speed is substantially increased. Circuits (PE.sub.2, 12, 13, S.sub.3 ', S.sub.4 ', S.sub.4 ') are provided which ensure that even in case of such a delayed decision, the correct reconstructed sample values (x.sub.0 ', x.sub.1 ', x.sub.2 ') are used.
    Type: Grant
    Filed: May 2, 1988
    Date of Patent: May 2, 1989
    Assignee: Alcatel N.V.
    Inventor: Peter Pirsch
  • Patent number: 4748503
    Abstract: A data reduction circuit employs a differential pulse code modulator for input video signals where the time-critical loop includes a loop subtractor (s2), a quantizer (q), and a loop delay element (v3), so that differential pulse code modulation can be performed at higher clock rates than with conventional architectures. With 2 .mu.m CMOS or N-channel MOS technology, for example, clock rates of 17 to 20 MHz are possible. The circuit includes a limiter circuit which applies the input video signals to the loop subtractor minuend input after processing the same. The output of the delay element in the loop is applied to inputs of a first adder, a vertical predictor and a constant multiplier, the multiplier receive a weighting factor equal to the square of a given weighting factor with the output of the multiplier applied to the subtrahend input of a first subtractor whose output is coupled to the input of the loop subtractor via a delay element.
    Type: Grant
    Filed: April 13, 1987
    Date of Patent: May 31, 1988
    Assignee: Deutsche ITT Industries GmbH
    Inventor: Peter Pirsch
  • Patent number: 4454506
    Abstract: The flicker which results from large intensity differences in adjacent scan lines of a symbol displayed in an interlaced-field format is reduced by a non-linear signal filter and signal generator. The disclosed filter and signal generator changes the intensity of a scan line adjacent to a scan line of a symbol in response to a detected predetermined intensity difference between the adjacent scan line and the symbol scan line.
    Type: Grant
    Filed: September 4, 1981
    Date of Patent: June 12, 1984
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Arun N. Netravali, Peter Pirsch
  • Patent number: 4420771
    Abstract: A series of words each representing one of at least M (M.gtoreq.3) different values is encoded by grouping the words into alternate runs of (1) a first, frequently occurring value, and (2) all other values. A coded representation of each run length as well as a representation of the non-frequent values which make up every other run are then combined in a predetermined sequence. Different code tables may be used to generate code words for each type of information.
    Type: Grant
    Filed: February 9, 1981
    Date of Patent: December 13, 1983
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventor: Peter Pirsch