Abstract: An apparatus for generating an oscillation signal is provided. The apparatus includes an input configured to receive a first reference oscillation signal, and a phase detector circuit configured to determine a phase drift of the first reference oscillation signal with respect to a second reference oscillation signal. Further, the apparatus includes a phase shifter circuit configured to generate the oscillation signal based on the first reference oscillation signal and a control signal. The control signal is based on the phase drift and a frequency control signal comprising control data for the phase shifter circuit for adjusting a frequency of the oscillation signal to a desired frequency.

Abstract: An apparatus for generating an oscillation signal is provided. The apparatus includes an input configured to receive a first reference oscillation signal, and a phase detector circuit configured to determine a phase drift of the first reference oscillation signal with respect to a second reference oscillation signal. Further, the apparatus includes a phase shifter circuit configured to generate the oscillation signal based on the first reference oscillation signal and a control signal. The control signal is based on the phase drift and a frequency control signal comprising control data for the phase shifter circuit for adjusting a frequency of the oscillation signal to a desired frequency.

Abstract: Method, systems, and circuitries are provided for generating an output signal with reduced spurs by dithering. A method to generate an output signal having a desired frequency based on a reference signal having a reference frequency includes receiving a desired phase shift between a next cycle of the output signal with respect to a next cycle of the reference signal. A mapping between respective code words and phase shifts is read. A first codeword mapped to a first phase shift that is lower in value to the desired phase shift is identified. A second codeword mapped to a second phase shift that is higher in value to the desired phase shift is identified. The method includes selecting either the first codeword or the second codeword and generating the output signal based on the selected codeword.

Abstract: In a modulation correction method, an adjusted amplitude is determined based on an amplitude between adjacent zero crossings of a modulated signal, the adjacent zero crossings are shifted to determine shifted zero crossings, and the modulated signal is adapted based on the adjusted amplitude and the shifted zero crossings to generate a corrected modulated signal corresponding to the modulated signal.

Abstract: A digitally controlled oscillator (DCO) circuit is disclosed. The DCO circuit comprises a tuning circuit configured to tune an oscillation frequency of the DCO circuit based on processing an integer tuning codeword and a fractional tuning codeword associated with an input tuning codeword. In some embodiments, the tuning circuit comprises an integer tuning circuit configured to process the integer tuning codeword and a fractional tuning circuit configured to process the fractional tuning codeword, in order to implement the input tuning codeword. In some embodiments, the integer tuning codeword comprises an integer tuning range associated therewith and the fractional tuning codeword comprises a fractional tuning range associated therewith. In some embodiments, the fractional tuning range associated with the fractional tuning codeword is configured to cover more than one step of the integer tuning range associated with the integer tuning codeword.

Abstract: A digitally controlled oscillator (DCO) circuit is disclosed. The DCO circuit comprises a tuning circuit configured to tune an oscillation frequency of the DCO circuit based on processing an integer tuning codeword and a fractional tuning codeword associated with an input tuning codeword. In some embodiments, the tuning circuit comprises an integer tuning circuit configured to process the integer tuning codeword and a fractional tuning circuit configured to process the fractional tuning codeword, in order to implement the input tuning codeword. In some embodiments, the integer tuning codeword comprises an integer tuning range associated therewith and the fractional tuning codeword comprises a fractional tuning range associated therewith. In some embodiments, the fractional tuning range associated with the fractional tuning codeword is configured to cover more than one step of the integer tuning range associated with the integer tuning codeword.

Abstract: Method, systems, and circuitries are provided for generating an output signal with reduced spurs by dithering. A method to generate an output signal having a desired frequency based on a reference signal having a reference frequency includes receiving a desired phase shift between a next cycle of the output signal with respect to a next cycle of the reference signal. A mapping between respective code words and phase shifts is read. A first codeword mapped to a first phase shift that is lower in value to the desired phase shift is identified. A second codeword mapped to a second phase shift that is higher in value to the desired phase shift is identified. The method includes selecting either the first codeword or the second codeword and generating the output signal based on the selected codeword.

Abstract: In a modulation correction method, an adjusted amplitude is determined based on an amplitude between adjacent zero crossings of a modulated signal, the adjacent zero crossings are shifted to determine shifted zero crossings, and the modulated signal is adapted based on the adjusted amplitude and the shifted zero crossings to generate a corrected modulated signal corresponding to the modulated signal.

Abstract: Techniques are disclosed to provide a data dependent delay for a multi-phase transmitter architectures. These techniques include identifying a current segment occupied by a symbol associated with in-phase (I) and quadrature phase (Q) data within a data constellation based upon the number of phases used. Once the segment is identified, vector components are calculated as a function of the segment used to re-map the symbol within the constellation defined in accordance with the number of phases. The data delay may be performed in the baseband or at the RF rate to time-align local oscillator clocks with the delayed data, which is represented as the calculated vector components, for transmission. Further modifications to the RF-DAC operation to facilitate operation with the multi-phase system are also disclosed.

Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.

Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.

Abstract: This application discusses, among other things, apparatus and methods for improving spurious frequency performance of digital-to-time converters (DTCs). In an example, a method can include receiving a code at selection logic of a digital-to-time converter at a first instant, selecting a first delay path of the DTC to provide a delay associated with the code, associating a second delay path with the code, receiving the code at the selection logic at a second instant, and selecting the second delay path of the DTC to provide the delay associated with the code.

Abstract: A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.

Abstract: A noise shaping circuit according to an example includes a forward signal path configured to generate an output signal based on an input signal, a feedback signal path configured to feed back a feedback signal based on the output signal to the forward signal path, and a dither generator configured to generate a dither signal and to couple the dither signal into the forward signal path to modify the input signal and into the feedback signal path. Employing a noise shaping circuit according to an example may improve an overall noise performance.

Abstract: A circuit according to an example includes a digital-to-time converter and a signal processing circuit coupled to the digital-to-time converter and configured to generate a processed signal derived from a signal provided to the signal processing circuit, the processed signal including a predetermined phase relation with respect to the signal provided to the signal processing circuit, wherein the circuit is configured to receive a reference signal and to generate an output signal based on the received reference signal. The a measurement circuit is configured to measure a delay between the output signal and the reference signal, wherein the output of the digital-to-time converter is coupled to a memory configured to store calibration data of the digital-to-time converter based on the measured delay.

Abstract: A circuit according to an example includes a digital-to-time converter configured to receive an oscillator signal and to generate a processed oscillator signal based on the received oscillator signal in response to a control signal, and a time-interleaved control circuit configured to generate the control signal based on a time-interleaved technique.

Abstract: A digital to time converter is disclosed and includes a code logic and an interpolator. The code logic is configured to receive a first phase signal and a second phase signal and generate a select signal according to the first phase signal and the second phase signal. The interpolator has a bank of inverters. The interpolator is configured to generate an interpolator signal based on the select signal and an input signal.

Abstract: A noise shaping circuit according to an example includes a forward signal path configured to generate an output signal based on an input signal, a feedback signal path configured to feed back a feedback signal based on the output signal to the forward signal path, and a dither generator configured to generate a dither signal and to couple the dither signal into the forward signal path to modify the input signal and into the feedback signal path. Employing a noise shaping circuit according to an example may improve an overall noise performance.

Abstract: A digital to time converter is disclosed and includes a code logic and an interpolator. The code logic is configured to receive a first phase signal and a second phase signal and generate a select signal according to the first phase signal and the second phase signal. The interpolator has a bank of inverters. The interpolator is configured to generate an interpolator signal based on the select signal and an input signal.

Abstract: A circuit according to an example includes a digital-to-time converter configured to receive an oscillator signal and to generate a processed oscillator signal based on the received oscillator signal in response to a control signal, and a time-interleaved control circuit configured to generate the control signal based on a time-interleaved technique.